[U-Boot] [U-boot] [Patch 2/6] ARM: keystone2: clock: add K2E clock support
Murali Karicheri
m-karicheri2 at ti.com
Thu Sep 4 16:08:09 CEST 2014
On 07/15/2014 05:59 PM, Ivan Khoronzhuk wrote:
> From: Hao Zhang<hzhang at ti.com>
>
> This patch adds clock definitions and commands to support Keystone2
> K2E SOC.
>
> Signed-off-by: Hao Zhang<hzhang at ti.com>
> Signed-off-by: Ivan Khoronzhuk<ivan.khoronzhuk at ti.com>
> ---
> arch/arm/cpu/armv7/keystone/Makefile | 1 +
> arch/arm/cpu/armv7/keystone/clock-k2e.c | 101 +++++++++++++++++++++++++
> arch/arm/cpu/armv7/keystone/clock.c | 2 +
> arch/arm/cpu/armv7/keystone/cmd_clock.c | 31 ++++++--
> arch/arm/include/asm/arch-keystone/clock-k2e.h | 68 +++++++++++++++++
> arch/arm/include/asm/arch-keystone/clock.h | 4 +
> include/configs/ks2_evm.h | 2 +-
> 7 files changed, 203 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm/cpu/armv7/keystone/clock-k2e.c
> create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2e.h
>
> diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile
> index 74c5160..f8519c0 100644
> --- a/arch/arm/cpu/armv7/keystone/Makefile
> +++ b/arch/arm/cpu/armv7/keystone/Makefile
> @@ -9,6 +9,7 @@ obj-y += init.o
> obj-y += psc.o
> obj-y += clock.o
> obj-$(CONFIG_SOC_K2HK) += clock-k2hk.o
> +obj-$(CONFIG_SOC_K2E) += clock-k2e.o
> obj-y += cmd_clock.o
> obj-y += cmd_mon.o
> obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_nav.o
> diff --git a/arch/arm/cpu/armv7/keystone/clock-k2e.c b/arch/arm/cpu/armv7/keystone/clock-k2e.c
> new file mode 100644
> index 0000000..42092e1
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/keystone/clock-k2e.c
> @@ -0,0 +1,101 @@
> +/*
> + * Keystone2: get clk rate for K2E
> + *
> + * (C) Copyright 2012-2014
> + * Texas Instruments Incorporated,<www.ti.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include<common.h>
> +#include<asm/arch/clock.h>
> +#include<asm/arch/clock_defs.h>
> +
> +const struct keystone_pll_regs keystone_pll_regs[] = {
> + [CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
> + [PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
> + [DDR3_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
> +};
> +
> +/**
> + * pll_freq_get - get pll frequency
> + * Fout = Fref * NF(mult) / NR(prediv) / OD
> + * @pll: pll identifier
> + */
> +static unsigned long pll_freq_get(int pll)
> +{
> + unsigned long mult = 1, prediv = 1, output_div = 2;
> + unsigned long ret;
> + u32 tmp, reg;
> +
> + if (pll == CORE_PLL) {
> + ret = external_clk[sys_clk];
> + if (pllctl_reg_read(pll, ctl)& PLLCTL_PLLEN) {
> + /* PLL mode */
> + tmp = __raw_readl(KS2_MAINPLLCTL0);
> + prediv = (tmp& PLL_DIV_MASK) + 1;
> + mult = (((tmp& PLLM_MULT_HI_SMASK)>> 6) |
> + (pllctl_reg_read(pll, mult)&
> + PLLM_MULT_LO_MASK)) + 1;
> + output_div = ((pllctl_reg_read(pll, secctl)>>
> + PLL_CLKOD_SHIFT)& PLL_CLKOD_MASK) + 1;
> +
> + ret = ret / prediv / output_div * mult;
> + }
> + } else {
> + switch (pll) {
> + case PASS_PLL:
> + ret = external_clk[pa_clk];
> + reg = KS2_PASSPLLCTL0;
> + break;
> + case DDR3_PLL:
> + ret = external_clk[ddr3_clk];
> + reg = KS2_DDR3APLLCTL0;
> + break;
> + default:
> + return 0;
> + }
> +
> + tmp = __raw_readl(reg);
> +
Please remove this line as below is part of this and should be in a
block IMO. With this change,
Acked-by: Murali Karicheri <m-karicheri2 at ti.com>
> + if (!(tmp& PLLCTL_BYPASS)) {
> + /* Bypass disabled */
> + prediv = (tmp& PLL_DIV_MASK) + 1;
> + mult = ((tmp>> PLL_MULT_SHIFT)& PLL_MULT_MASK) + 1;
> + output_div = ((tmp>> PLL_CLKOD_SHIFT)&
> + PLL_CLKOD_MASK) + 1;
> + ret = ((ret / prediv) * mult) / output_div;
> + }
> + }
> +
> + return ret;
> +}
> +
> +unsigned long clk_get_rate(unsigned int clk)
> +{
> + switch (clk) {
> + case core_pll_clk: return pll_freq_get(CORE_PLL);
> + case pass_pll_clk: return pll_freq_get(PASS_PLL);
> + case ddr3_pll_clk: return pll_freq_get(DDR3_PLL);
> + case sys_clk0_1_clk:
> + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1);
> + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2);
> + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3);
> + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4);
> + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2;
> + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3;
> + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4;
> + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6;
> + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8;
> + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12;
> + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24;
> + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3;
> + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4;
> + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6;
> + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c
> index 42b664b..03c1d9f 100644
> --- a/arch/arm/cpu/armv7/keystone/clock.c
> +++ b/arch/arm/cpu/armv7/keystone/clock.c
> @@ -106,6 +106,7 @@ void init_pll(const struct pll_init_data *data)
>
> tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN);
>
> +#ifndef CONFIG_SOC_K2E
> } else if (data->pll == TETRIS_PLL) {
> bwadj = pllm>> 1;
> /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */
> @@ -156,6 +157,7 @@ void init_pll(const struct pll_init_data *data)
> * only applicable for Kepler
> */
> setbits_le32(KS2_MISC_CTRL, KS2_ARM_PLL_EN);
> +#endif
> } else {
> setbits_le32(keystone_pll_regs[data->pll].reg1, PLLCTL_ENSAT);
> /*
> diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> index afd30f3..d97c95b 100644
> --- a/arch/arm/cpu/armv7/keystone/cmd_clock.c
> +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c
> @@ -14,10 +14,10 @@
> #include<asm/arch/psc_defs.h>
>
> struct pll_init_data cmd_pll_data = {
> - .pll = MAIN_PLL,
> - .pll_m = 16,
> - .pll_d = 1,
> - .pll_od = 2,
> + .pll = MAIN_PLL,
> + .pll_m = 16,
> + .pll_d = 1,
> + .pll_od = 2,
> };
>
> int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> @@ -27,12 +27,19 @@ int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>
> if (strncmp(argv[1], "pa", 2) == 0)
> cmd_pll_data.pll = PASS_PLL;
> +#ifndef CONFIG_SOC_K2E
> else if (strncmp(argv[1], "arm", 3) == 0)
> cmd_pll_data.pll = TETRIS_PLL;
> +#endif
> +#ifdef CONFIG_SOC_K2HK
> else if (strncmp(argv[1], "ddr3a", 5) == 0)
> cmd_pll_data.pll = DDR3A_PLL;
> else if (strncmp(argv[1], "ddr3b", 5) == 0)
> cmd_pll_data.pll = DDR3B_PLL;
> +#else
> + else if (strncmp(argv[1], "ddr3", 4) == 0)
> + cmd_pll_data.pll = DDR3_PLL;
> +#endif
> else
> goto pll_cmd_usage;
>
> @@ -51,11 +58,20 @@ pll_cmd_usage:
> return cmd_usage(cmdtp);
> }
>
> +#ifdef CONFIG_SOC_K2HK
> U_BOOT_CMD(
> pllset, 5, 0, do_pll_cmd,
> "set pll multiplier and pre divider",
> "<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
> );
> +#endif
> +#ifdef CONFIG_SOC_K2E
> +U_BOOT_CMD(
> + pllset, 5, 0, do_pll_cmd,
> + "set pll multiplier and pre divider",
> + "<pa|ddr3> <mult> <div> <OD>\n"
> +);
> +#endif
>
> int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> {
> @@ -79,7 +95,12 @@ U_BOOT_CMD(
> getclk, 2, 0, do_getclk_cmd,
> "get clock rate",
> "<clk index>\n"
> - "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n"
> +#ifdef CONFIG_SOC_K2HK
> + "See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
> +#endif
> +#ifdef CONFIG_SOC_K2E
> + "See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
> +#endif
> );
>
> int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
> diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
> new file mode 100644
> index 0000000..4147811
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
> @@ -0,0 +1,68 @@
> +/*
> + * K2E: Clock management APIs
> + *
> + * (C) Copyright 2012-2014
> + * Texas Instruments Incorporated,<www.ti.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __ASM_ARCH_CLOCK_K2E_H
> +#define __ASM_ARCH_CLOCK_K2E_H
> +
> +enum ext_clk_e {
> + sys_clk,
> + alt_core_clk,
> + pa_clk,
> + ddr3_clk,
> + mcm_clk,
> + pcie_clk,
> + sgmii_clk,
> + xgmii_clk,
> + usb_clk,
> + ext_clk_count /* number of external clocks */
> +};
> +
> +extern unsigned int external_clk[ext_clk_count];
> +
> +enum clk_e {
> + core_pll_clk,
> + pass_pll_clk,
> + ddr3_pll_clk,
> + sys_clk0_clk,
> + sys_clk0_1_clk,
> + sys_clk0_2_clk,
> + sys_clk0_3_clk,
> + sys_clk0_4_clk,
> + sys_clk0_6_clk,
> + sys_clk0_8_clk,
> + sys_clk0_12_clk,
> + sys_clk0_24_clk,
> + sys_clk1_clk,
> + sys_clk1_3_clk,
> + sys_clk1_4_clk,
> + sys_clk1_6_clk,
> + sys_clk1_12_clk,
> + sys_clk2_clk,
> + sys_clk3_clk
> +};
> +
> +#define KS2_CLK1_6 sys_clk0_6_clk
> +
> +/* PLL identifiers */
> +enum pll_type_e {
> + CORE_PLL,
> + PASS_PLL,
> + DDR3_PLL,
> +};
> +
> +#define CORE_PLL_800 {CORE_PLL, 16, 1, 2}
> +#define CORE_PLL_1000 {CORE_PLL, 20, 1, 2}
> +#define CORE_PLL_1200 {CORE_PLL, 24, 1, 2}
> +#define PASS_PLL_1000 {PASS_PLL, 20, 1, 2}
> +#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
> +#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
> +#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
> +#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h
> index c7da352..1513c76 100644
> --- a/arch/arm/include/asm/arch-keystone/clock.h
> +++ b/arch/arm/include/asm/arch-keystone/clock.h
> @@ -16,6 +16,10 @@
> #include<asm/arch/clock-k2hk.h>
> #endif
>
> +#ifdef CONFIG_SOC_K2E
> +#include<asm/arch/clock-k2e.h>
> +#endif
> +
> #define MAIN_PLL CORE_PLL
>
> #include<asm/types.h>
> diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
> index 29f0b9b..43db581 100644
> --- a/include/configs/ks2_evm.h
> +++ b/include/configs/ks2_evm.h
> @@ -80,7 +80,7 @@
> #define CONFIG_SPI_FLASH_STMICRO
> #define CONFIG_DAVINCI_SPI
> #define CONFIG_CMD_SPI
> -#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_LPSC_EMIF25_SPI)
> +#define CONFIG_SYS_SPI_CLK clk_get_rate(KS2_CLK1_6)
> #define CONFIG_SF_DEFAULT_SPEED 30000000
> #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
> #define CONFIG_SYS_SPI0
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