[U-Boot] [PATCH v2 3/4] imx: mx6solosabresd: Add the i.MX6Solo SABRESD board support

Ye.Li B37916 at freescale.com
Tue Sep 9 08:50:35 CEST 2014


The i.MX6solo SABRE-SD board configuration has the following
difference with i.MX6dl sabre-sd:

- DDR bus width: 32bit
- DDR capacity:  512M

Signed-off-by: Ye.Li <B37916 at freescale.com>
---
Changes since v1:
- Remove the "nosmp" kernel parameter, since kernel can detect cores number by SCU.
- Rework the short log subject

 board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg |  106 ++++++++++++++++++++
 configs/mx6solosabresd_defconfig                   |    3 +
 include/configs/mx6sabre_common.h                  |    4 +
 3 files changed, 113 insertions(+), 0 deletions(-)
 create mode 100644 board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
 create mode 100644 configs/mx6solosabresd_defconfig

diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
new file mode 100644
index 0000000..c886d66
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
@@ -0,0 +1,106 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343 at freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000030
+DATA 4 0x020e04c0 0x00000030
+DATA 4 0x020e04c4 0x00000030
+DATA 4 0x020e04c8 0x00000030
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000030
+DATA 4 0x020e0770 0x00000030
+DATA 4 0x020e0778 0x00000030
+DATA 4 0x020e077c 0x00000030
+DATA 4 0x020e0470 0x00000030
+DATA 4 0x020e0474 0x00000030
+DATA 4 0x020e0478 0x00000030
+DATA 4 0x020e047c 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b083c 0x42190219
+DATA 4 0x021b0840 0x017B0177
+DATA 4 0x021b0848 0x4B4D4E4D
+DATA 4 0x021b0850 0x3F3E2D36
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b0004 0x0002002D
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x3F435313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x00431023
+DATA 4 0x021b0040 0x00000017
+DATA 4 0x021b0000 0x83190000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b0004 0x0002556D
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig
new file mode 100644
index 0000000..d41754d
--- /dev/null
+++ b/configs/mx6solosabresd_defconfig
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg,MX6S,DEFAULT_FDT_FILE=\"imx6dl-sabresd.dtb\",DDR_MB=512"
+CONFIG_ARM=y
+CONFIG_TARGET_MX6SABRESD=y
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index e59a3b4..cf43404 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -11,6 +11,10 @@
 
 #define CONFIG_MX6
 
+#ifdef CONFIG_MX6S
+#define CONFIG_MX6DL
+#endif
+
 #include "mx6_common.h"
 #include <linux/sizes.h>
 
-- 
1.7.4.1



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