[U-Boot] [PATCH] imx6: add Bachmann OT1200 board
Stefano Babic
sbabic at denx.de
Mon Sep 15 17:32:45 CEST 2014
Hi Christian,
On 15/09/2014 08:37, Christian Gmeiner wrote:
> 2014-09-09 16:41 GMT+02:00 Christian Gmeiner <christian.gmeiner at gmail.com>:
>> This patch adds support for the OT1200 series of devices.
>>
>> Following components are used in u-boot:
>> + ethernet
>> + i2c
>> + emmc
>> + gpio
>>
>> The main difference between the different models of the OT1200
>> series is how ethernet is connected (directly to a switch or
>> to a normal phy).
>>
>> Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
>> ---
>> arch/arm/Kconfig | 4 +
>> board/bachmann/ot1200/Kconfig | 23 ++++
>> board/bachmann/ot1200/MAINTAINERS | 6 +
>> board/bachmann/ot1200/Makefile | 9 ++
>> board/bachmann/ot1200/ot1200.c | 262 ++++++++++++++++++++++++++++++++++++++
>> configs/ot1200_defconfig | 3 +
>> include/configs/ot1200.h | 195 ++++++++++++++++++++++++++++
>> 7 files changed, 502 insertions(+)
>> create mode 100644 board/bachmann/ot1200/Kconfig
>> create mode 100644 board/bachmann/ot1200/MAINTAINERS
>> create mode 100644 board/bachmann/ot1200/Makefile
>> create mode 100644 board/bachmann/ot1200/ot1200.c
>> create mode 100644 configs/ot1200_defconfig
>> create mode 100644 include/configs/ot1200.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 22f0f09..c93dcb6 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -412,6 +412,9 @@ config TARGET_HUMMINGBOARD
>> config TARGET_TQMA6
>> bool "TQ Systems TQMa6 board"
>>
>> +config TARGET_OT1200
>> + bool "Bachmann OT1200"
>> +
>> config OMAP34XX
>> bool "OMAP34XX SoC"
>>
>> @@ -564,6 +567,7 @@ source "board/atmel/at91sam9rlek/Kconfig"
>> source "board/atmel/at91sam9x5ek/Kconfig"
>> source "board/atmel/sama5d3_xplained/Kconfig"
>> source "board/atmel/sama5d3xek/Kconfig"
>> +source "board/bachmann/ot1200/Kconfig"
>> source "board/balloon3/Kconfig"
>> source "board/barco/titanium/Kconfig"
>> source "board/bluegiga/apx4devkit/Kconfig"
>> diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
>> new file mode 100644
>> index 0000000..55a825d
>> --- /dev/null
>> +++ b/board/bachmann/ot1200/Kconfig
>> @@ -0,0 +1,23 @@
>> +if TARGET_OT1200
>> +
>> +config SYS_CPU
>> + string
>> + default "armv7"
>> +
>> +config SYS_BOARD
>> + string
>> + default "ot1200"
>> +
>> +config SYS_VENDOR
>> + string
>> + default "bachmann"
>> +
>> +config SYS_SOC
>> + string
>> + default "mx6"
>> +
>> +config SYS_CONFIG_NAME
>> + string
>> + default "ot1200"
>> +
>> +endif
>> diff --git a/board/bachmann/ot1200/MAINTAINERS b/board/bachmann/ot1200/MAINTAINERS
>> new file mode 100644
>> index 0000000..ad75c24
>> --- /dev/null
>> +++ b/board/bachmann/ot1200/MAINTAINERS
>> @@ -0,0 +1,6 @@
>> +BACHMANN ELECTRONIC OT1200 BOARD
>> +M: Christian Gmeiner <christian.gmeiner at gmail.com>
>> +S: Maintained
>> +F: board/bachmann/ot1200
>> +F: include/configs/ot1200.h
>> +F: configs/ot1200*_defconfig
>> diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile
>> new file mode 100644
>> index 0000000..1bd42e8
>> --- /dev/null
>> +++ b/board/bachmann/ot1200/Makefile
>> @@ -0,0 +1,9 @@
>> +#
>> +# Copyright (C) 2012-2013, Guennadi Liakhovetski <lg at denx.de>
>> +# (C) Copyright 2012-2013 Freescale Semiconductor, Inc.
>> +# Copyright (C) 2013, Boundary Devices <info at boundarydevices.com>
>> +#
>> +# SPDX-License-Identifier: GPL-2.0+
>> +#
>> +
>> +obj-y := ot1200.o
>> diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
>> new file mode 100644
>> index 0000000..1c04f45
>> --- /dev/null
>> +++ b/board/bachmann/ot1200/ot1200.c
>> @@ -0,0 +1,262 @@
>> +/*
>> + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2014, Bachmann electronic GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/io.h>
>> +#include <asm/arch/clock.h>
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/arch/iomux.h>
>> +#include <malloc.h>
>> +#include <asm/arch/mx6-pins.h>
>> +#include <asm/imx-common/iomux-v3.h>
>> +#include <asm/imx-common/mxc_i2c.h>
>> +#include <asm/imx-common/sata.h>
>> +#include <asm/imx-common/boot_mode.h>
>> +#include <asm/arch/crm_regs.h>
>> +#include <mmc.h>
>> +#include <fsl_esdhc.h>
>> +#include <netdev.h>
>> +#include <i2c.h>
>> +#include <pca953x.h>
>> +#include <asm/gpio.h>
>> +#include <phy.h>
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
>> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
>> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +
>> +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
>> + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
>> + PAD_CTL_SRE_FAST | PAD_CTL_HYS)
>> +
>> +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
>> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
>> +
>> +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
>> + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>> +
>> +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
>> + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
>> + PAD_CTL_ODE | PAD_CTL_SRE_FAST)
>> +
>> +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
>> +
>> +int dram_init(void)
>> +{
>> + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
>> +
>> + return 0;
>> +}
>> +
>> +static iomux_v3_cfg_t const uart1_pads[] = {
>> + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_uart(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
>> +}
>> +
>> +static iomux_v3_cfg_t const enet_pads[] = {
>> + MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_enet(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
>> +}
>> +
>> +static iomux_v3_cfg_t const ecspi1_pads[] = {
>> + MX6_PAD_DISP0_DAT3__ECSPI3_SS0 | MUX_PAD_CTRL(SPI_PAD_CTRL),
>> + MX6_PAD_DISP0_DAT4__ECSPI3_SS1 | MUX_PAD_CTRL(SPI_PAD_CTRL),
>> + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
>> + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
>> + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
>> +};
>> +
>> +static void setup_iomux_spi(void)
>> +{
>> + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
>> +}
>> +
>> +int board_early_init_f(void)
>> +{
>> + setup_iomux_uart();
>> + setup_iomux_spi();
>> +
>> + return 0;
>> +}
>> +
>> +static iomux_v3_cfg_t const usdhc3_pads[] = {
>> + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
>> +};
>> +
>> +int board_mmc_getcd(struct mmc *mmc)
>> +{
>> + return 1;
>> +}
>> +
>> +struct fsl_esdhc_cfg usdhc_cfg[] = {
>> + {USDHC3_BASE_ADDR},
>> +};
>> +
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
>> + usdhc_cfg[0].max_bus_width = 8;
>> +
>> + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
>> +
>> + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
>> +}
>> +
>> +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
>> +
>> +/* I2C3 - IO expander */
>> +static struct i2c_pads_info i2c_pad_info2 = {
>> + .scl = {
>> + .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
>> + .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
>> + .gp = IMX_GPIO_NR(3, 17)
>> + },
>> + .sda = {
>> + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
>> + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
>> + .gp = IMX_GPIO_NR(3, 18)
>> + }
>> +};
>> +
>> +static iomux_v3_cfg_t const pwm_pad[] = {
>> + MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
>> +};
>> +
>> +static void leds_on(void)
>> +{
>> + /* turn on all possible leds connected via GPIO expander */
>> + i2c_set_bus_num(2);
>> + pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
>> + pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
>> +}
>> +
>> +static void backlight_lcd_off(void)
>> +{
>> + unsigned gpio = IMX_GPIO_NR(2, 0);
>> + gpio_direction_output(gpio, 0);
>> +
>> + gpio = IMX_GPIO_NR(2, 3);
>> + gpio_direction_output(gpio, 0);
>> +}
>> +
>> +int board_eth_init(bd_t *bis)
>> +{
>> + uint32_t base = IMX_FEC_BASE;
>> + struct mii_dev *bus = NULL;
>> + struct phy_device *phydev = NULL;
>> + int ret;
>> +
>> + setup_iomux_enet();
>> +
>> + bus = fec_get_miibus(base, -1);
>> + if (!bus)
>> + return 0;
>> + /* scan phy 0 and 5 */
>> + phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
>> + if (!phydev) {
>> + free(bus);
>> + return 0;
>> + }
>> +
>> + /* depending on the phy address we can detect our board version */
>> + if (phydev->addr == 0) {
>> + setenv("boardver", "");
>> + } else {
>> + setenv("boardver", "mr");
>> + }
>> +
>> + printf("using phy at %d\n", phydev->addr);
>> + ret = fec_probe(bis, -1, base, bus, phydev);
>> + if (ret) {
>> + printf("FEC MXC: %s:failed\n", __func__);
>> + free(phydev);
>> + free(bus);
>> + }
>> + return 0;
>> +}
>> +
>> +int board_init(void)
>> +{
>> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
>> + int reg;
>> +
>> + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>> +
>> + backlight_lcd_off();
>> +
>> + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
>> +
>> + leds_on();
>> +
>> + /* enable ecspi3 clocks */
>> + reg = __raw_readl(&mxc_ccm->CCGR1);
>> + reg |= MXC_CCM_CCGR1_ECSPI3S_MASK;
>> + writel(reg, &mxc_ccm->CCGR1);
>> +
>> + setup_sata();
>> +
>> + return 0;
>> +}
>> +
>> +int checkboard(void)
>> +{
>> + puts("Board: "CONFIG_SYS_BOARD"\n");
>> + return 0;
>> +}
>> +
>> +#ifdef CONFIG_CMD_BMODE
>> +static const struct boot_mode board_boot_modes[] = {
>> + /* 4 bit bus width */
>> + {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
>> + {NULL, 0},
>> +};
>> +#endif
>> +
>> +int misc_init_r(void)
>> +{
>> +#ifdef CONFIG_CMD_BMODE
>> + add_board_boot_modes(board_boot_modes);
>> +#endif
>> + return 0;
>> +}
>> diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
>> new file mode 100644
>> index 0000000..11797ce
>> --- /dev/null
>> +++ b/configs/ot1200_defconfig
>> @@ -0,0 +1,3 @@
>> +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q"
>> +CONFIG_ARM=y
>> +CONFIG_TARGET_OT1200=y
>> diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
>> new file mode 100644
>> index 0000000..fa21874
>> --- /dev/null
>> +++ b/include/configs/ot1200.h
>> @@ -0,0 +1,195 @@
>> +/*
>> + * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
>> + * Copyright (C) 2014 Bachmann electronic GmbH
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +#include "mx6_common.h"
>> +#define CONFIG_MX6
>> +#define CONFIG_DISPLAY_CPUINFO
>> +#define CONFIG_DISPLAY_BOARDINFO
>> +
>> +#include <asm/arch/imx-regs.h>
>> +#include <asm/imx-common/gpio.h>
>> +
>> +#define CONFIG_CMDLINE_TAG
>> +#define CONFIG_SETUP_MEMORY_TAGS
>> +#define CONFIG_INITRD_TAG
>> +#define CONFIG_REVISION_TAG
>> +#define CONFIG_SYS_GENERIC_BOARD
>> +
>> +/* Size of malloc() pool */
>> +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
>> +
>> +#define CONFIG_BOARD_EARLY_INIT_F
>> +#define CONFIG_MISC_INIT_R
>> +#define CONFIG_MXC_GPIO
>> +
>> +/* FUSE Configs */
>> +#define CONFIG_CMD_FUSE
>> +#define CONFIG_MXC_OCOTP
>> +
>> +/* UART Configs */
>> +#define CONFIG_MXC_UART
>> +#define CONFIG_MXC_UART_BASE UART1_BASE
>> +
>> +/* SF Configs */
>> +#define CONFIG_CMD_SF
>> +#define CONFIG_SPI_FLASH
>> +#define CONFIG_SPI_FLASH_STMICRO
>> +#define CONFIG_SPI_FLASH_WINBOND
>> +#define CONFIG_SPI_FLASH_MACRONIX
>> +#define CONFIG_SPI_FLASH_SST
>> +#define CONFIG_MXC_SPI
>> +#define CONFIG_SF_DEFAULT_BUS 2
>> +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(1, 3)<<8))
>> +#define CONFIG_SF_DEFAULT_SPEED 25000000
>> +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
>> +
>> +/* IO expander */
>> +#define CONFIG_PCA953X
>> +#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20
>> +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} }
>> +#define CONFIG_CMD_PCA953X
>> +#define CONFIG_CMD_PCA953X_INFO
>> +
>> +/* I2C Configs */
>> +#define CONFIG_CMD_I2C
>> +#define CONFIG_SYS_I2C
>> +#define CONFIG_SYS_I2C_MXC
>> +#define CONFIG_SYS_I2C_SPEED 100000
>> +
>> +/* OCOTP Configs */
>> +#define CONFIG_CMD_IMXOTP
>> +#define CONFIG_IMX_OTP
>> +#define IMX_OTP_BASE OCOTP_BASE_ADDR
>> +#define IMX_OTP_ADDR_MAX 0x7F
>> +#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA
>> +#define IMX_OTPWRITE_ENABLED
>> +
>> +/* MMC Configs */
>> +#define CONFIG_FSL_ESDHC
>> +#define CONFIG_FSL_USDHC
>> +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
>> +#define CONFIG_SYS_FSL_USDHC_NUM 2
>> +
>> +#define CONFIG_MMC
>> +#define CONFIG_CMD_MMC
>> +#define CONFIG_GENERIC_MMC
>> +#define CONFIG_BOUNCE_BUFFER
>> +
>> +#ifdef CONFIG_MX6Q
>> +#define CONFIG_CMD_SATA
>> +#endif
>> +
>> +/*
>> + * SATA Configs
>> + */
>> +#ifdef CONFIG_CMD_SATA
>> +#define CONFIG_DWC_AHSATA
>> +#define CONFIG_SYS_SATA_MAX_DEVICE 1
>> +#define CONFIG_DWC_AHSATA_PORT_ID 0
>> +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
>> +#define CONFIG_LBA48
>> +#define CONFIG_LIBATA
>> +#endif
>> +
>> +
>> +#define CONFIG_CMD_PING
>> +#define CONFIG_CMD_DHCP
>> +#define CONFIG_CMD_MII
>> +#define CONFIG_CMD_NET
>> +#define CONFIG_FEC_MXC
>> +#define CONFIG_MII
>> +#define IMX_FEC_BASE ENET_BASE_ADDR
>> +#define CONFIG_FEC_XCV_TYPE MII100
>> +#define CONFIG_ETHPRIME "FEC"
>> +#define CONFIG_FEC_MXC_PHYADDR 0x5
>> +#define CONFIG_PHYLIB
>> +#define CONFIG_PHY_SMSC
>> +
>> +/* Miscellaneous commands */
>> +#define CONFIG_CMD_BMODE
>> +#define CONFIG_CMD_SETEXPR
>> +
>> +/* allow to overwrite serial and ethaddr */
>> +#define CONFIG_ENV_OVERWRITE
>> +#define CONFIG_CONS_INDEX 1
>> +#define CONFIG_BAUDRATE 115200
>> +
>> +/* Command definition */
>> +#include <config_cmd_default.h>
>> +
>> +#undef CONFIG_CMD_IMLS
>> +
>> +#define CONFIG_BOOTDELAY 2
>> +
>> +#define CONFIG_PREBOOT ""
>> +
>> +#define CONFIG_LOADADDR 0x12000000
>> +#define CONFIG_SYS_TEXT_BASE 0x17800000
>> +
>> +/* Miscellaneous configurable options */
>> +#define CONFIG_SYS_LONGHELP
>> +#define CONFIG_SYS_HUSH_PARSER
>> +#define CONFIG_SYS_CBSIZE 1024
>> +
>> +/* Print Buffer Size */
>> +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
>> +#define CONFIG_SYS_MAXARGS 16
>> +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
>> +
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +
>> +#define CONFIG_CMDLINE_EDITING
>> +
>> +/* Physical Memory Map */
>> +#define CONFIG_NR_DRAM_BANKS 1
>> +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
>> +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
>> +
>> +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
>> +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
>> +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
>> +
>> +#define CONFIG_SYS_INIT_SP_OFFSET \
>> + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>> +#define CONFIG_SYS_INIT_SP_ADDR \
>> + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
>> +
>> +/* FLASH and environment organization */
>> +#define CONFIG_SYS_NO_FLASH
>> +
>> +#define CONFIG_ENV_IS_IN_SPI_FLASH
>> +#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */
>> +#define CONFIG_ENV_OFFSET (1024 * 1024)
>> +#define CONFIG_ENV_SECT_SIZE (64 * 1024) /* M25P16 has an erase size of 64 KiB */
>> +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
>> +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
>> +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
>> +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
>> +
>> +#define CONFIG_OF_LIBFDT
>> +#define CONFIG_CMD_BOOTZ
>> +
>> +#ifndef CONFIG_SYS_DCACHE_OFF
>> +#define CONFIG_CMD_CACHE
>> +#endif
>> +
>> +#define CONFIG_CMD_BOOTZ
>> +#define CONFIG_SUPPORT_RAW_INITRD
>> +
>> +/* FS Configs */
>> +#define CONFIG_CMD_EXT3
>> +#define CONFIG_CMD_EXT4
>> +#define CONFIG_DOS_PARTITION
>> +#define CONFIG_CMD_FS_GENERIC
>> +
>> +#define CONFIG_BOOTP_SERVERIP
>> +#define CONFIG_BOOTP_BOOTFILE
>> +
>> +#endif /* __CONFIG_H */
>> --
>> 1.9.3
>>
>
> ping
> --
Sorry, you're right. I am checking all patches that came in last weeks.
I see yours, I will check it soon.
Best regards,
Stefano Babic
--
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