[U-Boot] [PATCH] imx6: fix pl301_mx6qper1_bch clock gating setup

[Anatolij Gustschin]

Current code sets reserved CG1 bits instead of CG6 bits
for pl301_mx6qper1_bch clock. Fix it.

Signed-off-by: Anatolij Gustschin <agust at denx.de>
Cc: Heiko Schocher <hs at denx.de>
Cc: Stefan Roese <sr at denx.de>
Cc: Tim Harvey <tharvey at gateworks.com>
---
 board/aristainetos/aristainetos.c       |    2 +-
 board/barco/titanium/titanium.c         |    2 +-
 board/gateworks/gw_ventana/gw_ventana.c |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index 3bfcf5b..bb946b5 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -433,7 +433,7 @@ static void setup_gpmi_nand(void)
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
index 84a7b84..bcf45a2 100644
--- a/board/barco/titanium/titanium.c
+++ b/board/barco/titanium/titanium.c
@@ -177,7 +177,7 @@ static void setup_gpmi_nand(void)
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index a222921..b51c104 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -259,7 +259,7 @@ static void setup_gpmi_nand(void)
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 		     MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
-		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+		     MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
 
 	/* enable apbh clock gating */
 	setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
-- 
1.7.9.5