[U-Boot] [PATCH 29/35] arm: socfpga: cache: Define cacheline size

[Pavel Machek]

On Mon 2014-09-15 13:06:22, Marek Vasut wrote:
> The Cortex-A9 has 32-byte long L1 cachelines. Define this value.
> 
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Chin Liang See <clsee at altera.com>
> Cc: Dinh Nguyen <dinguyen at altera.com>
> Cc: Albert Aribaud <albert.u.boot at aribaud.net>
> Cc: Tom Rini <trini at ti.com>
> Cc: Wolfgang Denk <wd at denx.de>

Acked-by: Pavel Machek <pavel at denx.de>

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