[U-Boot] [PATCH 00/35][RFC] arm: socfpga: Usability fixes

[Dinh Nguyen]

On 09/16/2014 04:46 PM, Marek Vasut wrote:
> On Tuesday, September 16, 2014 at 11:35:38 PM, dinguyen wrote:
>> On Tue, 16 Sep 2014, Marek Vasut wrote:
>>> On Tuesday, September 16, 2014 at 06:28:52 PM, Dinh Nguyen wrote:
>>>> On 09/16/2014 08:18 AM, Pavel Machek wrote:
>>>>> Hi!
>>>>>
>>>>> On Mon 2014-09-15 13:05:53, Marek Vasut wrote:
>>>>>> This entire RFC series is the first stab at making SoCFPGA usable
>>>>>> with mainline U-Boot again. There are still some bits missing, but
>>>>>> in general, this allows me to use mainline U-Boot on my SoCFPGA
>>>>>> systems. The big missing part is the SPL generation, which still
>>>>>> needs a lot of additional work.
>>>>>>
>>>>>> This set contains patches for a few subsystems, bu the most part is
>>>>>> the SoCFPGA chip support.
>>>>>>
>>>>>> Most of the patches should be in good shape already, so I wonder if
>>>>>> the RFC tag is really necessary.
>>>>>
>>>>> Just... I earlier today I tested Marek's git tree based on this
>>>>> series, and it works well for me on board similar to sockit.
>>>>>
>>>>> So
>>>>>
>>>>> Tested-by: Pavel Machek <pavel at denx.de>
>>>>>
>>>>> Thanks and best regards,
>>>>>
>>>>> 									
> Pavel
>>>>
>>>> I applied all the patches to v2014.10-rc2, and I see that the watchdog
>>>> has been enabled and it's getting reset:
>>>>
>>>> U-Boot 2014.10-rc2-00139-g70e9e3e (Sep 16 2014 - 11:21:38)
>>>>
>>>> CPU:   Altera SoCFPGA Platform
>>>> BOARD: Altera SoCFPGA Cyclone5 Board
>>>>
>>>>        Watchdog enabled
>>>>
>>>> DRAM:
>>>> U-Boot SPL 2013.01.01-00019-g9cce15f (Jul 18 2013 - 13:05:43)
>>>> SDRAM : Initializing MMR registers
>>>> SDRAM : Calibrating PHY
>>>> SEQ.C: Preparing to start memory calibration
>>>> SEQ.C: CALIBRATION PASSED
>>>> ALTERA DWMMC: 0
>>>> reading u-boot.img
>>>> reading u-boot.img
>>>>
>>>>
>>>> U-Boot 2014.10-rc2-00139-g70e9e3e (Sep 16 2014 - 11:21:38)
>>>>
>>>> CPU:   Altera SoCFPGA Platform
>>>> BOARD: Altera SoCFPGA Cyclone5 Board
>>>>
>>>>        Watchdog enabled
>>>>
>>>> DRAM:
>>> This doesn't seem like a WDT problem. How much DRAM is there on that kit
>>> ? In any case, try this:
>>>
>>> 1) Edit arch/arm/cpu/armv7/socfpga/misc.c
>>> 2) Locate call to get_ram_size()
>>> 3) Replace this function call with the size of your DRAM in bytes.
>>>
>>>    (that is, make it "gd->ram_size = 128 * 1024 * 1024;" if you have
>>>    128MiB)
>>>
>>> I suspect get_ram_size() on socfpga is still broken in mainline and
>>> causes this crash you observe.
>>>
>>> btw you don't happen to have a spare CV and AV kits you could send me, so
>>> I can do the testing rounds on them too, do you ?
>>
>> What board are doing your testing on? The Arrow Sockit?
> 
> DENX MCVEVK and I also have the SoCKIT here. Pavel has something funny at home, 
> which I prefer to not know ;-)
> 
>> I also see this error print:
>>
>> U-Boot 2014.10-rc2-00139-g70e9e3e-dirty (Sep 16 2014 - 16:26:56)
>>
>> CPU:   Altera SoCFPGA Platform
>> BOARD: Altera SoCFPGA Cyclone5 Board
>>        Watchdog enabled
>> DRAM:  1 GiB
>> WARNING: Caches not enabled
> 
> This needs resolving. The I/D caches are enabled too late so we get this splat. 
> I'll cook a patch for that.
> 
>> Using default environment
>>
>> In:    serial
>> Out:   serial
>> Err:   serial
>> Net:   dwmac.ff702000
>> Error: dwmac.ff702000 address not set.
>> ^^^^^
>>
>> Do you see this on your side? I can track it down...
> 
> Use
> => setenv ethaddr 00:ma:ca:dd:re:ss
> => saveenv

ah yes...I added a CONFIG_ETHADDR since "saveenv" is not enabled yet.

Sorry for the noise, I was expecting
"Warning: failed to set MAC address"

Dinh