[U-Boot] [PATCH] socfpga: Enable DWMMC for SOCFPGA

[Chin Liang See]

To enable the DesignWare MMC controller driver support
for SOCFPGA Cyclone5 dev kit

Signed-off-by: Chin Liang See <clsee at altera.com>
Cc: Dinh Nguyen <dinguyen at altera.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Tom Rini <trini at ti.com>
Cc: Albert Aribaud <albert.u.boot at aribaud.net>
Cc: Wolfgang Denk <wd at denx.de>
---
 include/configs/socfpga_cyclone5.h |   18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 32175b7..f9fafac 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -252,6 +252,24 @@
 /* Clocks source frequency to watchdog timer */
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
 
+/*
+ * MMC support
+ */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_SDMMC_BASE		(SOCFPGA_SDMMC_ADDRESS)
+#define CONFIG_SDMMC_HOST_HS
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH	1024
+#define CONFIG_SOCFPGA_DWMMC_DRVSEL	3
+#define CONFIG_SOCFPGA_DWMMC_SMPSEL	0
+#define CONFIG_BOUNCE_BUFFER
+/* using smaller max blk cnt to avoid flooding the limited stack we have */
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT     256
+#endif	/* CONFIG_MMC */
 
 /*
  * SPL "Second Program Loader" aka Initial Software
-- 
1.7.9.5