[U-Boot] [PATCH 47/51] arm: socfpga: Move cache_enable to CPU code

[Marek Vasut]

Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Dinh Nguyen <dinguyen at altera.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Tom Rini <trini at ti.com>
Cc: Albert Aribaud <albert.u.boot at aribaud.net>
Cc: Wolfgang Denk <wd at denx.de>
---
 arch/arm/cpu/armv7/socfpga/misc.c       | 10 ++++++++++
 board/altera/socfpga/socfpga_cyclone5.c |  3 ---
 2 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/socfpga/misc.c b/arch/arm/cpu/armv7/socfpga/misc.c
index e0c7dc1..85aaf92 100644
--- a/arch/arm/cpu/armv7/socfpga/misc.c
+++ b/arch/arm/cpu/armv7/socfpga/misc.c
@@ -33,6 +33,16 @@ int dram_init(void)
 	return 0;
 }
 
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
 /*
  * DesignWare Ethernet initialization
  */
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 6b98277..0f81d89 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -34,9 +34,6 @@ int board_early_init_f(void)
  */
 int board_init(void)
 {
-	icache_enable();
-	dcache_enable();
-
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-- 
2.0.0