[U-Boot] [WIP PATCH 4/4 v2] arm: socfpga: Don't enable dcache (because of cadence SPI driver problem)

[Stefan Roese]

The Cadence SPI driver currently has some problems when the dcache is enabled.
As a work-around until this problem is fixed in the SPI driver, lets not
enable the dcache on the socfpga platforms. As its also done in the
rocketboards version.

Signed-off-by: Stefan Roese <sr at denx.de>
Cc: Chin Liang See <clsee at altera.com>
Cc: Dinh Nguyen <dinguyen at altera.com>
Cc: Vince Bridgers <vbridger at altera.com>
Cc: Marek Vasut <marex at denx.de>
Cc: Pavel Machek <pavel at denx.de>
Cc: Michael Trimarchi <michael at amarulasolutions.com>
---
 board/altera/socfpga/socfpga_cyclone5.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c
index 10f15e0..3f19d89 100644
--- a/board/altera/socfpga/socfpga_cyclone5.c
+++ b/board/altera/socfpga/socfpga_cyclone5.c
@@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev)
 int board_init(void)
 {
 	icache_enable();
+#if 0 // test-only: disable dcache for now as it causes problems with the SPI driver
 	dcache_enable();
+#endif
 
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-- 
2.1.0