[U-Boot] [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212

[qiang.zhao at freescale.com]

On 09/27/2014 12:02 AM, York Sun wrote:
> -----Original Message-----
> From: Sun York-R58495
> Sent: Saturday, September 27, 2014 12:02 AM
> To: Zhao Qiang-B45475; u-boot at lists.denx.de
> Cc: Xie Xiaobo-R63061
> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212
> 
> On 09/25/2014 10:55 PM, Zhao Qiang-B45475 wrote:
> >
> > On 9/26/14 1:01 PM, York Sun wrote:
> >
> >> -----Original Message-----
> >> From: Sun York-R58495
> >> Sent: Friday, September 26, 2014 1:01 PM
> >> To: Zhao Qiang-B45475; u-boot at lists.denx.de
> >> Cc: Xie Xiaobo-R63061; Zhao Qiang-B45475
> >> Subject: Re: [PATCH 2/2] powerpc/mpc85xx: modify erratum A007212
> >>
> >> On 9/25/14 9:37 PM, "Zhao Qiang" <B45475 at freescale.com> wrote:
> >>
> >>> T2080 v1.0 has this errata while v1.1 has fixed this errata by
> >>> hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and
> >>> SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't
> >>> run the a007212 errata_workaround.
> >>>
> >>> Signed-off-by: Zhao Qiang <B45475 at freescale.com>
> >>> ---
> >>
> >>
> >> Qiang,
> >>
> >> I don't agree with your analysis.
> >>
> >> This workaround has two parts. One part is to to disable DDR PLL in
> RCW.
> >> The second part is to detect DDR PLL is disabled and to implement the
> >> software workaround to bring DDR up. U-boot has the second part, it
> >> is safe to apply to all versions for affected SoC. I put in the
> comments.
> >> Your patch detects the SVR and decide if the workaround should be
> applied.
> >> This is wrong. It should detect if DDR PLL is disabled. In case an
> >> old RCW is used, you don't want to end up with a dead board because
> >> DDR is disabled.
> >
> > OK , got it , I will modify it for v2.
> > Thanks for you comment.
> >
> 
> Qiang,
> 
> I don't think you even need a patch for this. The logic for u-boot code
> is:
> 
> Regardless of the SVR, the workaround is not be applied if RCW doesn't
> disable DDR PLL.
> Regardless of the SVR, the workaround is and should be applied if RCW
> disables DDR PLL.

And how about the file arch/powerpc/cpu/mpc85xx/speed.c.
The code doesn't detect if the DDR PLL is disabled, it will config the mem_pll_rat.

> 
> York
Best Regards
Zhao Qiang