[U-Boot] [PATCH v3 4/5] imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset

[Stefano Babic]

On 09/09/2014 04:17, Ye.Li wrote:
> Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
> register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
> do not reset this PFD to avoid system hang. Customers may set this
> in DDR script or use BT_FREQ to select low freq boot.
> 
> Signed-off-by: Ye.Li <B37916 at freescale.com>
> ---

Applied to u-boot-imx, thanks !

Best regards,
Stefano Babic


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