[U-Boot] [PATCH v3 1/2] ARM: Add workaround for Cortex-A9 errata 845369

[nitin.garg at freescale.com]

From: Nitin Garg <nitin.garg at freescale.com>

Under very rare timing circumstances, transition into
streaming mode might create a data corruption. Exists on
all Cortex-A9 revisions.

Signed-off-by: Nitin Garg <nitin.garg at freescale.com>
---

Changes in v3: None
Changes in v2: None

 README                     |    1 +
 arch/arm/cpu/armv7/start.S |    5 +++++
 2 files changed, 6 insertions(+)

diff --git a/README b/README
index b7c2a17..8976041 100644
--- a/README
+++ b/README
@@ -683,6 +683,7 @@ The following options need to be configured:
 		CONFIG_ARM_ERRATA_751472
 		CONFIG_ARM_ERRATA_794072
 		CONFIG_ARM_ERRATA_761320
+		CONFIG_ARM_ERRATA_845369
 
 		If set, the workarounds for these ARM errata are applied early
 		during U-Boot startup. Note that these options force the
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 5ed0f45..db77adb 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -164,6 +164,11 @@ ENTRY(cpu_init_cp15)
 	orr	r0, r0, #1 << 21	@ set bit #21
 	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_845369
+	mrc	p15, 0, r0, c15, c0, 1	@ read diagnostic register
+	orr	r0, r0, #1 << 22	@ set bit #22
+	mcr	p15, 0, r0, c15, c0, 1	@ write diagnostic register
+#endif
 
 	mov	r5, lr			@ Store my Caller
 	mrc	p15, 0, r1, c0, c0, 0	@ r1 has Read Main ID Register (MIDR)
-- 
1.7.9.5