[U-Boot] [PATCH] x86: link: Add PCH driver to support SPI Flash

[Simon Glass]

U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/cpu/coreboot/pci.c      | 11 +++++++++++
 arch/x86/dts/chromebook_link.dts |  2 +-
 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index fa415dd..67eb14c 100644
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -34,3 +34,14 @@ U_BOOT_DRIVER(pci_x86_drv) = {
 	.of_match	= pci_x86_ids,
 	.ops		= &pci_x86_ops,
 };
+
+static const struct udevice_id generic_pch_ids[] = {
+	{ .compatible = "intel,pch" },
+	{ }
+};
+
+U_BOOT_DRIVER(generic_pch_drv) = {
+	.name		= "pch",
+	.id		= UCLASS_PCH,
+	.of_match	= generic_pch_ids,
+};
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index b450c3c..7c7034c 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -181,7 +181,7 @@
 
 		pch {
 			reg = <0x0000f800 0 0 0 0>;
-			compatible = "intel,bd82x6x";
+			compatible = "intel,bd82x6x", "intel,pch";
 			u-boot,dm-pre-reloc;
 			#address-cells = <1>;
 			#size-cells = <1>;
-- 
2.2.0.rc0.207.ga3a616c