[U-Boot] [PATCH 2/2][v2] pci/layerscape: fix link and class issues to support ls2085a

[York Sun]

On 03/11/2015 07:58 PM, Minghuan Lian wrote:
> 1. LS2085a provides PCIE_LUT_DBG register rather than PCIE_LDBG
>    to show the link status, so the patch fixes it.
> 2. Increase the delay time to make sure that link training
>    has finished.
> 3. Return invalid value when accessing multi-function device
> 4. For LS2085a DBI_RO_WR_EN bit is cleared as default, so we
>    must set this bit before change DBI register value.
> 
> Signed-off-by: Roy Zang <tie-fei.zang at freescale.com>
> Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
> ---
> change log:
> v1-v2: no change
> 

Applied to fsl-qoriq master, awaiting upstream.

York