[U-Boot] [PATCHv2 2/9] arm: socfpga: arria10: add reset manager for Arria10

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen at opensource.altera.com>

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
---
v2: integrate into a5/c5 reset manager
---
 arch/arm/mach-socfpga/include/mach/reset_manager.h | 66 ++++++++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              | 47 ++++++++++++++-
 2 files changed, 112 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 666a2ef..ada1e39 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -14,7 +14,44 @@ void socfpga_bridges_reset(int enable);
 
 void socfpga_per_reset(u32 reset, int set);
 void socfpga_per_reset_all(void);
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void);
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+struct socfpga_reset_manager {
+	u32	stat;
+	u32	ramstat;
+	u32	miscstat;
+	u32	ctrl;
+	u32	hdsken;
+	u32	hdskreq;
+	u32	hdskack;
+	u32	counts;
+	u32	mpu_mod_rst;
+	u32	per0_mod_rst;
+	u32	per1_mod_rst;
+	u32	brg_mod_rst;
+	u32	sys_mod_rst;
+	u32	coldmodrst;
+	u32	nrstmodrst;
+	u32	dbgmodrst;
+	u32	mpuwarmmask;
+	u32	per0warmmask;
+	u32	per1warmmask;
+	u32	brgwarmmask;
+	u32	syswarmmask;
+	u32	nrstwarmmask;
+	u32	l3warmmask;
+	u32	tststa;
+	u32	tstscratch;
+	u32	hdsktimeout;
+	u32	hmcintr;
+	u32	hmcintren;
+	u32	hmcintrens;
+	u32	hmcintrenr;
+	u32	hmcgpout;
+	u32	hmcgpin;
+};
+#else
 struct socfpga_reset_manager {
 	u32	status;
 	u32	ctrl;
@@ -27,6 +64,7 @@ struct socfpga_reset_manager {
 	u32	misc_mod_reset;
 	u32	tstscratch;
 };
+#endif
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
 #define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
@@ -54,6 +92,33 @@ struct socfpga_reset_manager {
 #define RSTMGR_BANK(_reset)			\
 	(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
 
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+/*
+ * SocFPGA Arria10 reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+#else
 /*
  * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
  * 0 ... mpumodrst
@@ -73,6 +138,7 @@ struct socfpga_reset_manager {
 #define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 22)
 #define RSTMGR_DMA		RSTMGR_DEFINE(1, 28)
 #define RSTMGR_SDR		RSTMGR_DEFINE(1, 29)
+#endif
 
 /* Create a human-readable reference to SoCFPGA reset. */
 #define SOCFPGA_RESET(_name)	RSTMGR_##_name
diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-socfpga/reset_manager.c
index b6beaa2..b955d39 100644
--- a/arch/arm/mach-socfpga/reset_manager.c
+++ b/arch/arm/mach-socfpga/reset_manager.c
@@ -18,7 +18,51 @@ static const struct socfpga_reset_manager *reset_manager_base =
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Assert or de-assert SoCFPGA reset manager reset. */
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void socfpga_per_reset(u32 reset, int set)
+{
+	const void *reg;
+
+	if (RSTMGR_BANK(reset) == 0)
+		reg = &reset_manager_base->mpu_mod_rst;
+	else if (RSTMGR_BANK(reset) == 1)
+		reg = &reset_manager_base->per0_mod_rst;
+	else if (RSTMGR_BANK(reset) == 2)
+		reg = &reset_manager_base->per1_mod_rst;
+	else if (RSTMGR_BANK(reset) == 3)
+		reg = &reset_manager_base->brg_mod_rst;
+	else if (RSTMGR_BANK(reset) == 4)
+		reg = &reset_manager_base->sys_mod_rst;
+	else    /* Invalid reset register, do nothing */
+		return;
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Disable all the peripherals except L4 watchdog0 and L4 Timer 0.
+ */
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void)
+{
+	const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(WD0)) |
+			(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
+
+	unsigned mask_ecc_ocp = 0x0000FF00;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(~l4wd0, &reset_manager_base->per1_mod_rst);
+	setbits_le32(&reset_manager_base->per0_mod_rst, ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(&reset_manager_base->per0_mod_rst, mask_ecc_ocp);
+}
+#else
 void socfpga_per_reset(u32 reset, int set)
 {
 	const void *reg;
@@ -118,3 +162,4 @@ void socfpga_bridges_reset(int enable)
 	}
 }
 #endif
+#endif
-- 
2.6.2