[U-Boot] L2 Cache lockdown on ARM Cortex A9, Omap4 - Panda

[Daniel Sobański]

Hi guys,

I am looking for a way to do a partial cache L2 lockdown using U-boot on
Panda.
Is it possible? I've tried done it many different ways (..) but this looks
the most promising.
According to the TRM of A9 and PLC310 CC, it is needed to set some bits in
Auxiliary Control Registrer, and this should be done before the kernel
boots up?

Is my approach kind of right?

Cheers, D.