[U-Boot] [PATCHv2 1/9] arm: socfpga: arria10: add system manager defines

[Marek Vasut]

On Tuesday, December 01, 2015 at 05:48:31 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen at opensource.altera.com>
> 
> Add system manager defines for Arria10.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
> ---
> v2: clean up parenthesis

[...]

> +/* bit fields */
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX		(1<<0)
> +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO		(1<<1)
> +#define SYSMGR_ECC_OCRAM_EN		(1<<0)
> +#define SYSMGR_ECC_OCRAM_SERR		(1<<3)
> +#define SYSMGR_ECC_OCRAM_DERR		(1<<4)

Uh, so you have SYSMGR_FPGAINTF_USEFPGA and _SPIM0 here, which use the same
bit. How is this supposed to work ? Is this some specialty of A10 ?

> +#define SYSMGR_FPGAINTF_USEFPGA		0x1
> +#define SYSMGR_FPGAINTF_SPIM0		(1<<0)
> +#define SYSMGR_FPGAINTF_SPIM1		(1<<1)
> +#define SYSMGR_FPGAINTF_EMAC0		(1<<2)
> +#define SYSMGR_FPGAINTF_EMAC1		(1<<3)
> +#define SYSMGR_FPGAINTF_NAND		(1<<4)
> +#define SYSMGR_FPGAINTF_SDMMC		(1<<5)
> +
> +/* Enumeration: sysmgr::emacgrp::ctrl::physel::enum                       

There's way too many spaces at the end, past ::enum .

> */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
> +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003

[...]

> +#define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK    0x00000002
> +#define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK    0x00000002

You're mixing spaces and TABs just past the MSK part.

> +#define SYSMGR_A10_SDMMC_CTRL_SET(smplsel, drvsel)	\
> +	((((drvsel) << 0) & 0x7) | (((smplsel) << 4) & 0x70))
> +
> +#endif /* _SOCFPGA_SYSTEM_MANAGER_A10_H_ */