[U-Boot] [PATCH v7 0/2] Make most DDR non-secure in MMU while keep a small block secure

[York Sun]

This set is to change MMU tables so DDR is in non-secure mode that
non-secure master such as SDHC DMA can access the data. To mix
secure and non-secure MMU entries, the MMU tables themselves have
to be in secure memory. A small portion memory is reserved at the
end of DDR (before debug server and MC) to host secure application
and the MMU tables.

This is different from existing armv7 secure_ram_addr() solution.
U-boot can run in the middle of memory if the memory is large.
Having security memory at the very end simplifies MMU setup.

Tested on LS2085AQDS with a known non-secure master test.


Changes in v7:
  Rebase to recent master
  Update ls1043ardb ddr.c
  Add change to ls1043qds ddr.c
  Check exception level before setting secure memory
  Leave gd->arch.tlb_addr unused if secure memory is setup

Changes in v6:
  Move cmd_bdinfo change into this patch
  Move flag macros and comments of secure_ram into this patch
  Move cmd_bdinfo change to 1st patch in this set
  Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE

Changes in v5:
  Put ifdef where gd->secure_ram is used

Changes in v4:
  Drop RFC from patch prefix
  Drop excessive mmu table for secure ram for early MMU
  Update commit message accordingly
  Mark QBMan cacheable portal memory non-secure

Changes in v3:
  Put ifdef around secure_ram
  Move defining CONFIG_SYS_MEM_RESERVE_SECURE to patch 2/2
  Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE
  Sanity check gd->secure_ram before using
  Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
  Include ls1043ardb
  Modified commit message.

Changes in v2:
  Do not use CONFIG_SYS_MEM_TOP_HIDE mechanism
  Move gd->arch.secure_ram to gd->secure_ram.
  Change the calculation of gd->secure_ram accordingly.
  Chnage commit message slightly accordingly.

Changes in v1:
  Initial patch.
  Depends on http://patchwork.ozlabs.org/patch/540248/

York Sun (2):
  Reserve secure memory
  armv8: fsl-layerscape: Make DDR non secure in MMU tables

 README                                            |    8 ++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c           |  121 ++++++++++++++++++---
 arch/arm/include/asm/arch-fsl-layerscape/config.h |    6 +
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h    |   14 ++-
 board/freescale/ls1043aqds/ddr.c                  |    9 ++
 board/freescale/ls1043ardb/ddr.c                  |   15 +++
 board/freescale/ls2080a/ddr.c                     |   15 +++
 board/freescale/ls2080aqds/ddr.c                  |   15 +++
 board/freescale/ls2080ardb/ddr.c                  |   15 +++
 common/board_f.c                                  |    9 ++
 common/cmd_bdinfo.c                               |    6 +
 include/asm-generic/global_data.h                 |   14 +++
 12 files changed, 228 insertions(+), 19 deletions(-)

-- 
1.7.9.5