[U-Boot] [PATCH 1/1] fsl_qspi: Pet the watchdog while reading/writing

Alexander Stein alexander.stein at systec-electronic.com
Mon Dec 7 07:39:44 CET 2015


On Friday 04 December 2015 12:10:47, York Sun wrote:
> 
> On 12/03/2015 05:56 PM, Wang Huan-B18965 wrote:
> >> On 12/03/2015 01:49 AM, Wang Huan-B18965 wrote:
> >>
> >> <snip>
> >>
> >>>>
> >>>> The actual command which results in a watchdog reset is 'sf read
> >>>> 0x81040000 0x200000 0x400000'. Please note that this uses an external
> >>>> watchdog which is enabled by default and resets after ~1.5s. The
> >>>> command itself takes about 2s (taken from my watch).
> >>>>
> >>> [Alison Wang] I could not reproduce the issue. Maybe I don't have the
> >>> external watchdog which will reset after ~1.5s as Alexander mentioned.
> >>>
> >>> U-Boot 2015.10-00273-g7ee52af (Dec 03 2015 - 17:32:24 +0800)
> >>>
> >>> CPU:   Freescale LayerScape LS1021E, Version: 2.0, (0x87081120)
> >>> Clock Configuration:
> >>>        CPU0(ARMV7):1000 MHz,
> >>>        Bus:300  MHz, DDR:800  MHz (1600 MT/s data rate), Reset
> >>> Configuration Word (RCW):
> >>>        00000000: 0608000a 00000000 00000000 00000000
> >>>        00000010: 30000000 00007900 40025a00 21046000
> >>>        00000020: 00000000 00000000 00000000 20000000
> >>>        00000030: 20024800 881b7540 00000000 00000000
> >>> Model: LS1021A TWR Board
> >>> Board: LS1021ATWR
> >>> I2C:   ready
> >>> DRAM:  1 GiB
> >>> Using SERDES1 Protocol: 48 (0x30)
> >>> MMC:   FSL_SDHC: 0
> >>> SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB,
> >>> total 16 MiB
> >>> EEPROM: NXID v1
> >>> PCIe1: Root Complex no link, regs @ 0x3400000
> >>> PCIe2: disabled
> >>> In:    serial
> >>> Out:   serial
> >>> Err:   serial
> >>> SEC: RNG instantiated
> >>> SATA link 0 timeout.
> >>> AHCI 0001.0300 1 slots 1 ports ? Gbps 0x1 impl SATA mode
> >>> flags: 64bit ncq pm clo only pmp fbss pio slum part ccc Found 0
> >>> device(s).
> >>> SCSI:  Net:   eTSEC1 is in sgmii mode.
> >>> eTSEC2 is in sgmii mode.
> >>> eTSEC1, eTSEC2, eTSEC3 [PRIME]
> >>> => => sf probe
> >>> SF: Detected N25Q128 with page size 256 Bytes, erase size 64 KiB,
> >>> total 16 MiB => sf read 0x81040000 0x200000 0x400000 device 0 offset
> >>> 0x200000, size 0x400000
> >>> SF: 4194304 bytes @ 0x200000 Read: OK
> >>> =>
> >>
> >> Alison and Alexander,
> >>
> >> My concerns are
> >>
> >> Is the watchdog triggered reasonably?
> > [Alison Wang] I think as Alexander set the watchdog to 1s timeout, so the
> > trigger occurs at that time.

Well, 'set' is not exactly correct. It is 'set' by hardware (power sequencer), thus fixed in hardware. No way to change it.

> >> How long does it take to load the file?
> > [Alison Wang] About 2s.
> >> Is SPI running at reasonable speed?
> > [Alison Wang] Yes.
> >> Is there other similar situations such as loading large file off NOR
> >> flash?
> > [Alison Wang] If we don't set the watchdog to 1s timeout, both loading
> > Large file to serial flash or NOR flash, there is not such situation.
> > If we set the watchdog to 1s timeout, I think there are both such
> > situation.
> > 
> > Alexander, do you agree with my answer? Please give your comments too. :)

I can't test NOR, there is just none. But loading from TFTP works fine (about 3s download time), so it seems rather a QSPI driver problem.
Other answers are same for me.

> If an external watchdog is used, any long operation may trigger it.

Yep, especially there is no way to avoid that, despite petting it at reasonable intervals.

Best regards,
Alexander
-- 
Dipl.-Inf. Alexander Stein
SYS TEC electronic GmbH
alexander.stein at systec-electronic.com

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