[U-Boot] [PATCH 18/57] x86: ivybridge: Move GPIO init to the LPC init() method

[Simon Glass]

This init can happen in the driver also. Move it.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/cpu/ivybridge/cpu.c | 4 ----
 arch/x86/cpu/ivybridge/lpc.c | 3 +++
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 8827c2c..849b058 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -300,10 +300,6 @@ int print_cpuinfo(void)
 
 	gd->arch.pei_boot_mode = boot_mode;
 
-	/* TODO: Move this to the board or driver */
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-	x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
-
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c
index a445b03..d24aac6 100644
--- a/arch/x86/cpu/ivybridge/lpc.c
+++ b/arch/x86/cpu/ivybridge/lpc.c
@@ -633,6 +633,9 @@ static int bd82x6x_lpc_init(struct udevice *dev)
 	setbits_le32(RCB_REG(GCS), 1 >> 5);	/* No reset */
 	outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
 
+	dm_pci_write_config32(dev->parent, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+	dm_pci_write_config32(dev->parent, GPIO_CNTL, 0x10);
+
 	return 0;
 }
 
-- 
2.6.0.rc2.230.g3dd15c0