[U-Boot] [PATCH 52/57] x86: ivybridge: Convert EHCI init to use the DM PCI API

[Simon Glass]

Convert this code over to use the driver model PCI API. The easiest way to
do this is to iterate through the valid USB devices in the device tree.

Signed-off-by: Simon Glass <sjg at chromium.org>
---

 arch/x86/cpu/ivybridge/bd82x6x.c              | 26 ++++++++++++++++++++++--
 arch/x86/cpu/ivybridge/usb_ehci.c             | 29 ---------------------------
 arch/x86/dts/chromebook_link.dts              | 12 +++++++++++
 arch/x86/include/asm/arch-ivybridge/bd82x6x.h |  1 -
 4 files changed, 36 insertions(+), 32 deletions(-)
 delete mode 100644 arch/x86/cpu/ivybridge/usb_ehci.c

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c
index ff6d485..13ede5c 100644
--- a/arch/x86/cpu/ivybridge/bd82x6x.c
+++ b/arch/x86/cpu/ivybridge/bd82x6x.c
@@ -17,6 +17,7 @@
 #include <asm/arch/model_206ax.h>
 #include <asm/arch/pch.h>
 #include <asm/arch/sandybridge.h>
+#include <dm/uclass-internal.h>
 
 static int pch_revision_id = -1;
 static int pch_type = -1;
@@ -146,6 +147,24 @@ void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
 		return;
 }
 
+static void bd82x6x_usb_ehci_init(struct udevice *dev)
+{
+	u32 reg32;
+
+	/* Disable Wake on Disconnect in RMH */
+	reg32 = readl(RCB_REG(0x35b0));
+	reg32 |= 0x22;
+	writel(reg32, RCB_REG(0x35b0));
+
+	debug("EHCI: Setting up controller.. ");
+	dm_pci_read_config32(dev, PCI_COMMAND, &reg32);
+	reg32 |= PCI_COMMAND_MASTER;
+	/* reg32 |= PCI_COMMAND_SERR; */
+	dm_pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	debug("done.\n");
+}
+
 static int bd82x6x_probe(struct udevice *dev)
 {
 	const void *blob = gd->fdt_blob;
@@ -158,8 +177,11 @@ static int bd82x6x_probe(struct udevice *dev)
 	/* Cause the SATA device to do its init */
 	uclass_first_device(UCLASS_AHCI, &dev);
 
-	bd82x6x_usb_ehci_init(PCH_EHCI1_DEV);
-	bd82x6x_usb_ehci_init(PCH_EHCI2_DEV);
+	/* Set up the USB devices, being careful not to probe them yet */
+	for (uclass_find_first_device(UCLASS_USB, &dev);
+	     dev;
+	     uclass_find_next_device(&dev))
+		bd82x6x_usb_ehci_init(dev);
 
 	gma_node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_GMA);
 	if (gma_node < 0) {
diff --git a/arch/x86/cpu/ivybridge/usb_ehci.c b/arch/x86/cpu/ivybridge/usb_ehci.c
deleted file mode 100644
index da11aee..0000000
--- a/arch/x86/cpu/ivybridge/usb_ehci.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * From Coreboot
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * SPDX-License-Identifier:	GPL-2.0
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/pci.h>
-#include <asm/arch/pch.h>
-
-void bd82x6x_usb_ehci_init(pci_dev_t dev)
-{
-	u32 reg32;
-
-	/* Disable Wake on Disconnect in RMH */
-	reg32 = readl(RCB_REG(0x35b0));
-	reg32 |= 0x22;
-	writel(reg32, RCB_REG(0x35b0));
-
-	debug("EHCI: Setting up controller.. ");
-	reg32 = x86_pci_read_config32(dev, PCI_COMMAND);
-	reg32 |= PCI_COMMAND_MASTER;
-	/* reg32 |= PCI_COMMAND_SERR; */
-	x86_pci_write_config32(dev, PCI_COMMAND, reg32);
-
-	debug("done.\n");
-}
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index b54a545..6a4f7b3 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -12,6 +12,8 @@
 
 	aliases {
 		spi0 = "/pci/pch/spi";
+		usb0 = &usb_0;
+		usb1 = &usb_1;
 	};
 
 	config {
@@ -226,6 +228,16 @@
 			u-boot,dm-pre-reloc;
 		};
 
+		usb_1: usb at 1a,0 {
+			reg = <0x0000d800 0 0 0 0>;
+			compatible = "ehci-pci";
+		};
+
+		usb_0: usb at 1d,0 {
+			reg = <0x0000e800 0 0 0 0>;
+			compatible = "ehci-pci";
+		};
+
 		pch at 1f,0 {
 			reg = <0x0000f800 0 0 0 0>;
 			compatible = "intel,bd82x6x", "intel,pch";
diff --git a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
index bb3a6c9..5959717 100644
--- a/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
+++ b/arch/x86/include/asm/arch-ivybridge/bd82x6x.h
@@ -7,7 +7,6 @@
 #ifndef _ASM_ARCH_BD82X6X_H
 #define _ASM_ARCH_BD82X6X_H
 
-void bd82x6x_usb_ehci_init(pci_dev_t dev);
 void bd82x6x_usb_xhci_init(pci_dev_t dev);
 int gma_func0_init(struct udevice *dev, const void *blob, int node);
 
-- 
2.6.0.rc2.230.g3dd15c0