[U-Boot] [PATCH 43/57] x86: ivybridge: Convert enable_usb_bar() to use DM PCI API

[Bin Meng]

Hi Simon,

On Tue, Dec 8, 2015 at 11:39 AM, Simon Glass <sjg at chromium.org> wrote:
> Convert this function over to use the driver model PCI API. In this case
> we want to avoid using the real PCI devices since they have not yet been
> probed. Instead, write directly to their PCI configuration address.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>

Reviewed-by: Bin Meng <bmeng.cn at gmail.com>

One question below.

>  arch/x86/cpu/ivybridge/cpu.c | 42 +++++++++++++++++++++---------------------
>  1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
> index 95a9db5..b79a726 100644
> --- a/arch/x86/cpu/ivybridge/cpu.c
> +++ b/arch/x86/cpu/ivybridge/cpu.c
> @@ -134,33 +134,33 @@ int arch_cpu_init_dm(void)
>   *
>   * This is used to speed up the resume path.
>   */
> -static void enable_usb_bar(void)
> +static void enable_usb_bar(struct udevice *bus)
>  {
>         pci_dev_t usb0 = PCH_EHCI1_DEV;
>         pci_dev_t usb1 = PCH_EHCI2_DEV;
>         pci_dev_t usb3 = PCH_XHCI_DEV;
> -       u32 cmd;
> +       ulong cmd;
>
>         /* USB Controller 1 */
> -       x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
> -                              PCH_EHCI0_TEMP_BAR0);
> -       cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
> +       pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
> +                            PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
> +       pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
>         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
> -       x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
> +       pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
>
> -       /* USB Controller 1 */
> -       x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
> -                              PCH_EHCI1_TEMP_BAR0);
> -       cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
> +       /* USB Controller 2 */
> +       pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
> +                            PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
> +       pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
>         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
> -       x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
> +       pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
>
> -       /* USB3 Controller */
> -       x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
> -                              PCH_XHCI_TEMP_BAR0);
> -       cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
> +       /* USB3 Controller 1 */
> +       pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
> +                            PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
> +       pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
>         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
> -       x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
> +       pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);

What is the purpose to do this temporary BAR assignment?

>  }
>
>  static int report_bist_failure(void)
> @@ -178,7 +178,7 @@ int print_cpuinfo(void)
>  {
>         enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
>         char processor_name[CPU_MAX_NAME_LEN];
> -       struct udevice *dev, *lpc;
> +       struct udevice *dev, *lpc, *pch;
>         const char *name;
>         uint32_t pm1_cnt;
>         uint16_t pm1_sts;
> @@ -211,12 +211,12 @@ int print_cpuinfo(void)
>         /* Early chipset init required before RAM init can work */
>         uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
>
> -       ret = uclass_first_device(UCLASS_PCH, &dev);
> +       ret = uclass_first_device(UCLASS_PCH, &pch);
>         if (ret)
>                 return ret;
> -       if (!dev)
> +       if (!pch)
>                 return -ENODEV;
> -       ret = pch_init(dev);
> +       ret = pch_init(pch);
>         if (ret)
>                 return ret;
>
> @@ -266,7 +266,7 @@ int print_cpuinfo(void)
>
>         /* Prepare USB controller early in S3 resume */
>         if (boot_mode == PEI_BOOT_RESUME)
> -               enable_usb_bar();
> +               enable_usb_bar(pch->parent);
>
>         gd->arch.pei_boot_mode = boot_mode;
>
> --

Regards,
Bin