[U-Boot] [PATCH v7 2/2] armv8: fsl-layerscape: Make DDR non secure in MMU tables

[York Sun]

On 12/05/2015 03:57 AM, York Sun wrote:
> DDR has been set as secure in MMU tables. Non-secure master such
> as SDHC DMA cannot access data correctly. Mixing secure and non-
> secure MMU entries requirs the MMU tables themselves in secure
> memory. This patch moves MMU tables into a secure DDR area.
> 
> Early MMU tables are changed to set DDR as non-secure. A new
> table is added into final MMU tables so secure memory can have
> 2MB granuality.
> 
> gd->secure_ram tracks the location of this secure memory. For
> ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
> banks. gd->secure_ram needs to be maintained before using. This
> maintenance is board-specific, depending on the SoC and memory
> bank of the secure memory falls into.
> 
> Signed-off-by: York Sun <yorksun at freescale.com>
> 
> ---
> 
> Changes in v7:
>   Rebase to recent master
>   Update ls1043ardb ddr.c
>   Add change to ls1043qds ddr.c
>   Check exception level before setting secure memory
>   Leave gd->arch.tlb_addr unused if secure memory is setup
> 
> Changes in v6:
>   Move cmd_bdinfo change to 1st patch in this set
>   Rearrange #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
> 
> Changes in v5:
>   Put ifdef where gd->secure_ram is used
> 
> Changes in v4:
>   Drop RFC from patch prefix
>   Drop excessive mmu table for secure ram for early MMU
>   Update commit message accordingly
>   Mark QBMan cacheable portal memory non-secure
> 
> Changes in v3:
>   Replace CONFIG_FSL_PPA_RESERVED_DRAM_SIZE with CONFIG_SYS_MEM_RESERVE_SECURE
>   Sanity check gd->secure_ram before using
>   Define CONFIG_SYS_MEM_RESERVE_SECURE in SoC header file
>   Include ls1043ardb
>   Modified commit message.
> 
> Changes in v2:
>   Move gd->arch.secure_ram to gd->secure_ram.
>   Change the calculation of gd->secure_ram accordingly.
>   Chnage commit message slightly accordingly.
> 
> Changes in v1: None
> 

Applied to fsl-qoriq master. Awaiting upstream.

York