[U-Boot] [PATCH] arm: socfpga: Fix emac1 doesn't work on socdk board

[Chin Liang See]

Hi Shengjiang,

On Fri, 2015-12-18 at 15:13 +0800, shengjiangwu wrote:
> Updated pinmux group MIXED1IO[0-13] for RGMII1.
> Updated EMAC1 clock.
> 
> Signed-off-by: shengjiangwu <shengjiangwu at icloud.com>
> Cc: Chin Liang See <clsee at altera.com>
> Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
> Cc: Dinh Nguyen <dinh.linux at gmail.com>
> Cc: Pavel Machek <pavel at denx.de>
> Cc: Marek Vasut <marex at denx.de>
> Cc: Stefan Roese <sr at denx.de>

Thanks for the patch.

> ---
>  board/altera/cyclone5-socdk/qts/pinmux_config.h |   28 +++++++++++--
> ----------
>  board/altera/cyclone5-socdk/qts/pll_config.h    |    4 ++--
>  2 files changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> index 33cf1fd..442b1e0 100644
> --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
> @@ -72,20 +72,20 @@ const u8 sys_mgr_init_table[] = {
>  	0, /* GENERALIO29 */
>  	0, /* GENERALIO30 */
>  	0, /* GENERALIO31 */
> -	0, /* MIXED1IO0 */
> -	1, /* MIXED1IO1 */
> -	1, /* MIXED1IO2 */
> -	1, /* MIXED1IO3 */
> -	1, /* MIXED1IO4 */
> -	0, /* MIXED1IO5 */
> -	0, /* MIXED1IO6 */
> -	0, /* MIXED1IO7 */
> -	1, /* MIXED1IO8 */
> -	1, /* MIXED1IO9 */
> -	1, /* MIXED1IO10 */
> -	1, /* MIXED1IO11 */
> -	0, /* MIXED1IO12 */
> -	0, /* MIXED1IO13 */
> +	2, /* MIXED1IO0 */
> +	2, /* MIXED1IO1 */
> +	2, /* MIXED1IO2 */
> +	2, /* MIXED1IO3 */
> +	2, /* MIXED1IO4 */
> +	2, /* MIXED1IO5 */
> +	2, /* MIXED1IO6 */
> +	2, /* MIXED1IO7 */
> +	2, /* MIXED1IO8 */
> +	2, /* MIXED1IO9 */
> +	2, /* MIXED1IO10 */
> +	2, /* MIXED1IO11 */
> +	2, /* MIXED1IO12 */
> +	2, /* MIXED1IO13 */
>  	0, /* MIXED1IO14 */
>  	1, /* MIXED1IO15 */
>  	1, /* MIXED1IO16 */
> diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
> b/board/altera/cyclone5-socdk/qts/pll_config.h
> index 3d621ed..42905f4 100644
> --- a/board/altera/cyclone5-socdk/qts/pll_config.h
> +++ b/board/altera/cyclone5-socdk/qts/pll_config.h
> @@ -31,7 +31,7 @@
>  #define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79
>  #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
>  #define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
> -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511
> +#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
>  #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
>  #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
>  #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
> @@ -65,7 +65,7 @@
>  #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
>  #define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
>  #define CONFIG_HPS_CLK_EMAC0_HZ 250000000
> -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
> +#define CONFIG_HPS_CLK_EMAC1_HZ 50000000

I believe the EMAC1 clock is still 250MHz which result of 25MHz *
(79+1) / (1+1) / (3+1).

Thanks
Chin Liang

>  #define CONFIG_HPS_CLK_USBCLK_HZ 200000000
>  #define CONFIG_HPS_CLK_NAND_HZ 50000000
>  #define CONFIG_HPS_CLK_SDMMC_HZ 200000000