[U-Boot] [PATCH] arm: socfpga: Fix QSPI doesn't work on socdk board

[圣江 吴]

Hi Chin,

The PLL settings are copied from previous version http://git.rocketboards.org/u-boot-socfpga.git, 

On Dec 17, 2015, at 11:45 PM, Chin Liang See <clsee at altera.com> wrote:

Hi Shengjiang,

On Fri, 2015-12-18 at 15:21 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu <shengjiangwu at icloud.com>
Cc: Chin Liang See <clsee at altera.com>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux at gmail.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Stefan Roese <sr at denx.de>
---
board/altera/cyclone5-socdk/qts/pinmux_config.h | 12 ++++++------
board/altera/cyclone5-socdk/qts/pll_config.h | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h
b/board/altera/cyclone5-socdk/qts/pinmux_config.h
index 442b1e0..06783dc 100644
--- a/board/altera/cyclone5-socdk/qts/pinmux_config.h
+++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h
@@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
       2, /* MIXED1IO12 */
       2, /* MIXED1IO13 */
       0, /* MIXED1IO14 */
-        1, /* MIXED1IO15 */
-        1, /* MIXED1IO16 */
-        1, /* MIXED1IO17 */
-        1, /* MIXED1IO18 */
-        0, /* MIXED1IO19 */
-        0, /* MIXED1IO20 */
+        3, /* MIXED1IO15 */
+        3, /* MIXED1IO16 */
+        3, /* MIXED1IO17 */
+        3, /* MIXED1IO18 */
+        3, /* MIXED1IO19 */
+        3, /* MIXED1IO20 */
       0, /* MIXED1IO21 */
       0, /* MIXED2IO0 */
 0, /* MIXED2IO1 */
diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index 42905f4..eccc705 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
-#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
@@ -32,7 +32,7 @@
#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3
#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
-#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1

Let's not change this as we are using mainpll for QSPI clock. Besides
that, the QSPI perpll will yield 500MHz which exceed the 400MHz max
clock.

Thanks
Chin Liang

OK, I will restore CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT as 511

Thanks ShengjiangWu
 


#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511