[U-Boot] [PATCH v2] arm: socfpga: Fix emac1 doesn't work on socdk board

[圣江 吴]

On Dec 18, 2015, at 12:46 AM, Chin Liang See <clsee at altera.com> wrote:

Hi Shengjiang,

On Fri, 2015-12-18 at 16:43 +0800, shengjiangwu wrote:
Updated pinmux group MIXED1IO[0-13] for RGMII1.
Updated EMAC1 clock.

Signed-off-by: shengjiangwu <shengjiangwu at icloud.com>
Cc: Chin Liang See <clsee at altera.com>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux at gmail.com>
Cc: Pavel Machek <pavel at denx.de>
Cc: Marek Vasut <marex at denx.de>
Cc: Stefan Roese <sr at denx.de>
---
Changes for v2:
- fixed wrong perpll for emac1
---
board/altera/cyclone5-socdk/qts/pll_config.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h
b/board/altera/cyclone5-socdk/qts/pll_config.h
index eccc705..5b754ac 100644
--- a/board/altera/cyclone5-socdk/qts/pll_config.h
+++ b/board/altera/cyclone5-socdk/qts/pll_config.h
@@ -65,7 +65,7 @@
#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666
#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
-#define CONFIG_HPS_CLK_EMAC1_HZ 50000000
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000


This is good. But I believe you miss the pinmux change here. You just
need to take the previous patch and made the change.

Thanks
Chin Liang

Sorry for not familiar with re-patch process. 
Best Regards
Shengjiangwu


#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
#define CONFIG_HPS_CLK_NAND_HZ 50000000
#define CONFIG_HPS_CLK_SDMMC_HZ 200000000