[U-Boot] [PATCH 2/2] m68k: add DM model serial driver
Angelo Dureghello
angelo at sysam.it
Sat Dec 19 14:43:49 CET 2015
Boards can now use DM serial driver, or still legacy mcf uart
driver version.
Add DM-related changes for AMCORE board, to use as a tested example.
Signed-off-by: Angelo Dureghello <angelo at sysam.it>
---
board/sysam/amcore/amcore.c | 33 +++++
configs/amcore_defconfig | 2 +
drivers/serial/mcfuart.c | 193 ++++++++++++++++++++++-------
include/dm/platform_data/serial_coldfire.h | 23 ++++
4 files changed, 207 insertions(+), 44 deletions(-)
create mode 100644 include/dm/platform_data/serial_coldfire.h
diff --git a/board/sysam/amcore/amcore.c b/board/sysam/amcore/amcore.c
index 42b7c23..523f374 100644
--- a/board/sysam/amcore/amcore.c
+++ b/board/sysam/amcore/amcore.c
@@ -9,6 +9,8 @@
*/
#include <common.h>
+#include <dm.h>
+#include <dm/platform_data/serial_coldfire.h>
#include <asm/immap.h>
#include <asm/io.h>
@@ -47,6 +49,26 @@ void fudelay(int usec)
asm volatile ("nop");
}
+/*
+ * allows a pre-console debug
+ * using some leds
+ */
+void debug_leds(unsigned short on)
+{
+ sim_t *sim = (sim_t *)(MMAP_SIM);
+ gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
+ unsigned short switch_on = on;
+
+ out_be16(&sim->par, 0x0000);
+ out_be16(&gpio->paddr, 0xffff);
+
+ switch_on = ~switch_on;
+ out_be16(&gpio->padat, switch_on);
+
+ for (;;)
+ ;
+}
+
phys_size_t initdram(int board_type)
{
u32 dramsize, RC;
@@ -99,3 +121,14 @@ phys_size_t initdram(int board_type)
return get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_SIZE);
}
+
+static struct coldfire_serial_platdata mcf5307_serial_plat = {
+ .base = CONFIG_SYS_UART_BASE,
+ .port = 0,
+ .baudrate = CONFIG_BAUDRATE,
+};
+
+U_BOOT_DEVICE(coldfire_serial) = {
+ .name = "serial_coldfire",
+ .platdata = &mcf5307_serial_plat,
+};
diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig
index ad69f0a..0cadc03 100644
--- a/configs/amcore_defconfig
+++ b/configs/amcore_defconfig
@@ -1,6 +1,8 @@
CONFIG_M68K=y
CONFIG_TARGET_AMCORE=y
CONFIG_SYS_PROMPT="amcore $ "
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FPGA is not set
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c
index 407354f..03a4d64 100644
--- a/drivers/serial/mcfuart.c
+++ b/drivers/serial/mcfuart.c
@@ -2,6 +2,9 @@
* (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew, Tsi-Chung.Liew at freescale.com.
*
+ * Modified to add device model (DM) support
+ * (C) Copyright 2015 Angelo Dureghello <angelo at sysam.it>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -11,101 +14,123 @@
*/
#include <common.h>
+#include <dm.h>
#include <serial.h>
#include <linux/compiler.h>
-
#include <asm/immap.h>
#include <asm/uart.h>
+#ifdef CONFIG_DM_SERIAL
+# include <dm/platform_data/serial_coldfire.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
extern void uart_port_conf(int port);
-static int mcf_serial_init(void)
+static int mcf_serial_init_common(uart_t *uart, int port_idx, int baudrate)
{
- volatile uart_t *uart;
u32 counter;
- uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
- uart_port_conf(CONFIG_SYS_UART_PORT);
+ uart_port_conf(port_idx);
/* write to SICR: SIM2 = uart mode,dcd does not affect rx */
- uart->ucr = UART_UCR_RESET_RX;
- uart->ucr = UART_UCR_RESET_TX;
- uart->ucr = UART_UCR_RESET_ERROR;
- uart->ucr = UART_UCR_RESET_MR;
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+ writeb(UART_UCR_RESET_ERROR, &uart->ucr);
+ writeb(UART_UCR_RESET_MR, &uart->ucr);
__asm__("nop");
- uart->uimr = 0;
+ writeb(0, &uart->uimr);
/* write to CSR: RX/TX baud rate from timers */
- uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
+ writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
- uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
- uart->umr = UART_UMR_SB_STOP_BITS_1;
+ writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
+ writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
/* Setting up BaudRate */
- counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
- counter = counter / gd->baudrate;
+ counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+ counter = counter / baudrate;
/* write to CTUR: divide counter upper byte */
- uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
+ writeb((u8)((counter & 0xff00) >> 8), &uart->ubg1);
/* write to CTLR: divide counter lower byte */
- uart->ubg2 = (u8) (counter & 0x00ff);
+ writeb((u8)(counter & 0x00ff), &uart->ubg2);
- uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
return (0);
}
+static void mcf_serial_setbrg_common(uart_t *uart, int baudrate)
+{
+ u32 counter;
+
+ /* Setting up BaudRate */
+ counter = (u32) ((gd->bus_clk / 32) + (baudrate / 2));
+ counter = counter / baudrate;
+
+ /* write to CTUR: divide counter upper byte */
+ writeb(((counter & 0xff00) >> 8), &uart->ubg1);
+ /* write to CTLR: divide counter lower byte */
+ writeb((counter & 0x00ff), &uart->ubg2);
+
+ writeb(UART_UCR_RESET_RX, &uart->ucr);
+ writeb(UART_UCR_RESET_TX, &uart->ucr);
+
+ writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
+}
+
+#ifndef CONFIG_DM_SERIAL
+
+static int mcf_serial_init(void)
+{
+ uart_t *uart_base;
+ int port_idx;
+
+ uart_base = (uart_t *)CONFIG_SYS_UART_BASE;
+ port_idx = CONFIG_SYS_UART_PORT;
+
+ return mcf_serial_init_common(uart_base, port_idx, gd->baudrate);
+}
+
static void mcf_serial_putc(const char c)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
if (c == '\n')
serial_putc('\r');
/* Wait for last character to go. */
- while (!(uart->usr & UART_USR_TXRDY)) ;
+ while (!(readb(&uart->usr) & UART_USR_TXRDY))
+ ;
- uart->utb = c;
+ writeb(c, &uart->utb);
}
static int mcf_serial_getc(void)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
/* Wait for a character to arrive. */
- while (!(uart->usr & UART_USR_RXRDY)) ;
- return uart->urb;
-}
+ while (!(readb(&uart->usr) & UART_USR_RXRDY))
+ ;
-static int mcf_serial_tstc(void)
-{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
-
- return (uart->usr & UART_USR_RXRDY);
+ return readb(&uart->urb);
}
static void mcf_serial_setbrg(void)
{
- volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
- u32 counter;
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
- /* Setting up BaudRate */
- counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
- counter = counter / gd->baudrate;
-
- /* write to CTUR: divide counter upper byte */
- uart->ubg1 = ((counter & 0xff00) >> 8);
- /* write to CTLR: divide counter lower byte */
- uart->ubg2 = (counter & 0x00ff);
+ mcf_serial_setbrg_common(uart, gd->baudrate);
+}
- uart->ucr = UART_UCR_RESET_RX;
- uart->ucr = UART_UCR_RESET_TX;
+static int mcf_serial_tstc(void)
+{
+ uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE;
- uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
+ return readb(&uart->usr) & UART_USR_RXRDY;
}
static struct serial_device mcf_serial_drv = {
@@ -128,3 +153,83 @@ __weak struct serial_device *default_serial_console(void)
{
return &mcf_serial_drv;
}
+
+#endif
+
+#ifdef CONFIG_DM_SERIAL
+
+static int coldfire_serial_probe(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+
+ return mcf_serial_init_common((uart_t *)plat->base,
+ plat->port, plat->baudrate);
+}
+
+static int coldfire_serial_putc(struct udevice *dev, const char ch)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)plat->base;
+
+ if (ch == '\n')
+ serial_putc('\r');
+
+ /* Wait for last character to go. */
+ while (!(readb(&uart->usr) & UART_USR_TXRDY))
+ ;
+
+ writeb(ch, &uart->utb);
+
+ return 0;
+}
+
+static int coldfire_serial_getc(struct udevice *dev)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ /* Wait for a character to arrive. */
+ while (!(readb(&uart->usr) & UART_USR_RXRDY))
+ ;
+
+ return readb(&uart->urb);
+}
+
+int coldfire_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ mcf_serial_setbrg_common(uart, baudrate);
+
+ return 0;
+}
+
+static int coldfire_serial_pending(struct udevice *dev, bool input)
+{
+ struct coldfire_serial_platdata *plat = dev->platdata;
+ uart_t *uart = (uart_t *)(plat->base);
+
+ if (input)
+ return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0;
+ else
+ return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1;
+
+ return 0;
+}
+
+static const struct dm_serial_ops coldfire_serial_ops = {
+ .putc = coldfire_serial_putc,
+ .pending = coldfire_serial_pending,
+ .getc = coldfire_serial_getc,
+ .setbrg = coldfire_serial_setbrg,
+};
+
+U_BOOT_DRIVER(serial_coldfire) = {
+ .name = "serial_coldfire",
+ .id = UCLASS_SERIAL,
+ .probe = coldfire_serial_probe,
+ .ops = &coldfire_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+#endif
diff --git a/include/dm/platform_data/serial_coldfire.h b/include/dm/platform_data/serial_coldfire.h
new file mode 100644
index 0000000..fc1ad71
--- /dev/null
+++ b/include/dm/platform_data/serial_coldfire.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2015 Angelo Dureghello <angelo at sysam.it>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __serial_coldfire_h
+#define __serial_coldfire_h
+
+/*
+ * struct coldfire_serial_platdata - information about a coldfire port
+ *
+ * @base: Uart port base register address
+ * @port: Uart port index, for cpu with pinmux for uart / gpio
+ * baudrtatre: Uart port baudrate
+ */
+struct coldfire_serial_platdata {
+ unsigned long base;
+ int port;
+ int baudrate;
+};
+
+#endif /* __serial_coldfire_h */
--
2.5.3
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