[U-Boot] [PATCH v3 1/4] mips: add base support for atheros ath79 based SOCs

[Marek Vasut]

On Saturday, December 26, 2015 at 06:35:35 PM, Marek Vasut wrote:
> On Saturday, December 26, 2015 at 04:48:57 PM, Wills Wang wrote:
> 
> [...]
> 
> > > The SPI flash is an IP block which just maps the SPI NOR into the
> > > address space, it doesn't use the CPU cache at all.
> > > 
> > > Maybe you don't even need to lock cachelines though, the AR9331 should
> > > have some internal SRAM, so just use that for stack. Do you have a
> > > proper datasheet for the Atheros MIPS chips ? I have some 320 pages
> > > datasheet for AR9331.
> > 
> > I don't find any description about internal SRAM in public datasheet.
> > About mapping SPI flash, there is a doubt, who fetch the instruction from
> > the SPI Nor flash to CPU pipe line when chip boot from SPI flash?
> > I guess that ROM code handle cache exception and load instruction/date
> > from SPI flash into cache.
> 
> I just pulled out the SPI NOR from the Arduino Yun I have here and
> connected an FPGA with SPI NOR emulator in there. All the chip does is it
> issues the fastread opcode to the SPI NOR when it boots. It does the same
> thing if you access the 0x9f000000..0x9fxxxxxx address range from the
> ancient U-Boot 1.1.x.
> 
> My impression is that the SPI NOR controller in the chip does a mapping
> between the SPI NOR and the memory mapped access to the 0x9fxxxxxx range.
> There is no caching involved in that, all of this is done internally in
> the SPI NOR block.
> 
> The mips24kc core should support locking cache lines , so if the SRAM is
> not available, this would have to do.

Ha, look at this [1]. risk @ #openwrt-devel at freenode pointed this location
out (thanks!)

[1] https://github.com/pepe2k/u-boot_mod/blob/master/u-
boot/cpu/mips/start.S#L652

Best regards,
Marek Vasut