[U-Boot] [PATCH v2 15/22] x86: ivybridge: Set up an MTRR for the video frame buffer

[Simon Glass]

Hi Bin,

On 3 January 2015 at 20:18, Bin Meng <bmeng.cn at gmail.com> wrote:
> Hi Simon,
>
> On Fri, Jan 2, 2015 at 7:18 AM, Simon Glass <sjg at chromium.org> wrote:
>> Set the frame buffer to write-combining. This makes it faster, although for
>> scrolling write-through is even faster for U-Boot.
>>
>> Signed-off-by: Simon Glass <sjg at chromium.org>
>> ---
>>
>> Changes in v2:
>> - Remove definition of 'ulong start' from this patch
>>
>>  arch/x86/cpu/ivybridge/gma.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivybridge/gma.c
>> index cf4f87c..6cf9654 100644
>> --- a/arch/x86/cpu/ivybridge/gma.c
>> +++ b/arch/x86/cpu/ivybridge/gma.c
>> @@ -12,6 +12,7 @@
>>  #include <fdtdec.h>
>>  #include <pci_rom.h>
>>  #include <asm/io.h>
>> +#include <asm/mtrr.h>
>>  #include <asm/pci.h>
>>  #include <asm/arch/pch.h>
>>  #include <asm/arch/sandybridge.h>
>> @@ -735,6 +736,7 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
>>         ulong start;
>>  #endif
>>         void *gtt_bar;
>> +       ulong base;
>>         u32 reg32;
>>         int ret;
>>
>> @@ -743,6 +745,11 @@ int gma_func0_init(pci_dev_t dev, struct pci_controller *hose,
>>         reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
>>         pci_write_config32(dev, PCI_COMMAND, reg32);
>>
>> +       /* Use write-combining for the graphics memory, 256MB */
>> +       base = pci_read_bar32(hose, dev, 2);
>> +       mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20);
>> +       mtrr_commit(true);
>> +
>>         gtt_bar = (void *)pci_read_bar32(pci_bus_to_hose(0), dev, 0);
>>         debug("GT bar %p\n", gtt_bar);
>>         ret = gma_pm_init_pre_vbios(gtt_bar);
>> --
>
> Do you have any comments regarding to what I said in
> http://lists.denx.de/pipermail/u-boot/2014-December/199955.html?

Ah yes I meant to say that I did look at a function to return the BAR
size, but it involves changing the BAR. I have a patch out to convert
PCI to driver model and there we will be able to store the size. So
perhaps we should revisit this later?

Regards,
Simon