[U-Boot] [PATCH 07/10] x86: Implement a cache for Memory Reference Code parameters

[Bin Meng]

Hi Simon,

On Mon, Jan 5, 2015 at 9:49 AM, Simon Glass <sjg at chromium.org> wrote:
> Hi Bin,
>
> On 4 January 2015 at 00:49, Bin Meng <bmeng.cn at gmail.com> wrote:
>> Hi Simon,
>>
>> On Tue, Dec 30, 2014 at 9:12 AM, Simon Glass <sjg at chromium.org> wrote:
>>> The memory reference code takes a very long time to 'train' its SDRAM
>>> interface, around half a second. To avoid this delay on every boot we can
>>> store the parameters from the last training sessions to speed up the next.
>>>
>>> Add an implementation of this, storing the training data in CMOS RAM and
>>> SPI flash.
>>
>> Is storing mrc data to cmos ram not enough, so that we must store it
>> to spi flash?
>
> It's about 3KB of data, so doesn't fit in CMOS.

Sorry but I did not get into the details of the codes, but if CMOS
cannot hold the whole MRC cache data, what information do we need save
in the CMOS? Can we just save them into SPI flash all toghether
without having CMOS?

[snip]

Regards,
Bin