[U-Boot] [PATCH v2 0/12] x86: Better support of coreboot

[Bin Meng]

In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.

Note this v2 patch series aims to better support coreboot, while v1
patch series just tried to resolve the issues seen on qemu. Several
issues are fixed to make coreboot support in U-Boot more robust.

See v1 patch discussion
@ http://lists.denx.de/pipermail/u-boot/2015-January/200140.html

The official qemu U-Boot support will come in the future. This patch
series have been tested with coreboot running on qemu and Intel Crown
Bay (my own unofficiall simple port, not in coreboot mainline) then
loading the U-Boot built with the new mechanism.

Changes in v2:
- Fix the CONFIG_COLLECT_TIMESTAMPS typo in the comment block
  and commit message
- Spell out TSC, MSR and PIT in the Kconfig help
- New patch to move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16
  to Kconfig
- New patch to hide ROM chip size when CONFIG_X86_RESET_VECTOR is
  not selected
- New patch to make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
- New patch to move coreboot specific defines from coreboot.h to Kconfig
- New patch to move CONFIG_SYS_CAR_xxx to Kconfig
- New patch to remove include/configs/coreboot.h
- New patch to make chromebook_link the default board for coreboot
- Leave CROS_EC defines unchanged in coreboot.h
- New patch to configure pci memory regions
- New patch to update REAME.x86 for coreboot support

Bin Meng (12):
  x86: coreboot: Set up timer base correctly
  x86: Allow a hardcoded TSC frequency provided by Kconfig
  x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to
    Kconfig
  x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
  x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
    configurable
  x86: coreboot: Move coreboot specific defines from coreboot.h to
    Kconfig
  x86: Move CONFIG_SYS_CAR_xxx to Kconfig
  x86: Remove include/configs/coreboot.h
  x86: Make chromebook_link the default board for coreboot
  x86: coreboot: Wrap cros_ec initialization
  x86: coreboot: Configure pci memory regions
  x86: Update REAME.x86 for coreboot support

 arch/x86/Kconfig                     |  32 +++++
 arch/x86/cpu/coreboot/Kconfig        |  11 ++
 arch/x86/cpu/coreboot/pci.c          |  30 ++++-
 arch/x86/cpu/coreboot/timestamp.c    |  33 +++---
 arch/x86/cpu/ivybridge/Kconfig       |   8 ++
 arch/x86/dts/Makefile                |   3 +-
 arch/x86/dts/chromebook_link.dts     | 220 ++++++++++++++++++++++++++++++++++-
 arch/x86/dts/link.dts                | 219 ----------------------------------
 arch/x86/lib/tsc_timer.c             |   8 +-
 board/coreboot/coreboot/Kconfig      |  27 ++++-
 board/coreboot/coreboot/MAINTAINERS  |   2 +-
 board/coreboot/coreboot/coreboot.c   |   2 +
 board/google/chromebook_link/Kconfig |   9 ++
 board/intel/crownbay/Kconfig         |   1 +
 configs/coreboot-x86_defconfig       |   1 -
 doc/README.x86                       |  35 ++++++
 include/configs/chromebook_link.h    |   7 +-
 include/configs/coreboot.h           |  75 ------------
 include/configs/crownbay.h           |   2 -
 19 files changed, 401 insertions(+), 324 deletions(-)
 create mode 100644 arch/x86/cpu/coreboot/Kconfig
 mode change 120000 => 100644 arch/x86/dts/chromebook_link.dts
 delete mode 100644 arch/x86/dts/link.dts
 delete mode 100644 include/configs/coreboot.h

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1.8.2.1