[U-Boot] [PATCH 1/3] samsung: board: support eMMC reset using DT

[Jaehoon Chung]

On 01/09/2015 08:23 AM, Sjoerd Simons wrote:
> On Thu, 2015-01-08 at 14:44 +0900, Joonyoung Shim wrote:
>> Some exynos boards require special handling of SD4_nRESET_OUT line for
>> eMMC memory to perform complete reboot e.g. Odroid X2/U3/XU3 boards.
>>
>> This will support eMMC reset using DT from reset_misc of samsung common
>> board file and each board files can support eMMC reset on non DT case.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> 
>> diff --git a/doc/device-tree-bindings/exynos/emmc-reset.txt b/doc/device-tree-bindings/exynos/emmc-reset.txt
>> new file mode 100644
>> index 0000000..e48e508
>> --- /dev/null
>> +++ b/doc/device-tree-bindings/exynos/emmc-reset.txt
>> @@ -0,0 +1,15 @@
>> +* Samsung eMMC reset
>> +
>> +Some exynos boards require special handling of SD4_nRESET_OUT line for eMMC
>> +memory to perform complete reboot.
> 
> Nitpick, on XU3 the line you apparently need to twiddle is
> SD0_nRESET_OUT.
> 
> Is this type of usage of this pin specific to the Odroid Exynos boards
> or potentially on more boards? (Sorry for the simple questions, but my
> exynos documentation just says the line exists not what its intended
> usage is). 

In case of Exynos4, eMMC can be used with sdhci controller or dw-mmc controller.
So Pin name should be used to SD0 or SD4.

But Exynos5 is only supported the dw-mmc controller.
(So eMMC is used pin-name as "SD0".)

Best Regards,
Jaehoon Chung
> 
> Fwiw, I did a quick check in the linux code and it doesn't seem to be
> using those pins for currently for any boards. However my X2 does
> successfully reset/reboot in u-boot and linux, so it seems optional
> there. The XU3 does fail to reset itself, so it seems required for that
> board.
> 
>> +Required properties:
>> +- compatible: should be "samsung,emmc-reset"
>> +- reset-gpio: gpio chip for eMMC reset.
>> +
>> +Example:
>> +
>> +emmc-reset {
>> +        compatible = "samsung,emmc-reset";
>> +        reset-gpio = <&gpk1 2 0>;
>> +};
> 
> 
> 
> 
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