[U-Boot] [PATCH v2 07/11] x86: dts: Add SPI flash MRC details for chromebook_link

[Bin Meng]

Hi Simon,

On Fri, Jan 9, 2015 at 11:30 AM, Simon Glass <sjg at chromium.org> wrote:
> Correct the SPI flash compatible string, add an alias and specify the
> position of the MRC cache, used to store SDRAM training settings for the
> Memory Reference Code.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v2:
> - Make changes to chromebook_link.dts since link.dts is gone
> - Use intel,ich-spi as the compatible string
>
>  arch/x86/dts/chromebook_link.dts |  15 ++-
>  arch/x86/dts/link.dts            | 229 +++++++++++++++++++++++++++++++++++++++
>  2 files changed, 243 insertions(+), 1 deletion(-)
>  create mode 100644 arch/x86/dts/link.dts
>
> diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
> index 9490b16..45ada61 100644
> --- a/arch/x86/dts/chromebook_link.dts
> +++ b/arch/x86/dts/chromebook_link.dts
> @@ -7,6 +7,10 @@
>         model = "Google Link";
>         compatible = "google,link", "intel,celeron-ivybridge";
>
> +       aliases {
> +               spi0 = "/spi";
> +       };
> +
>         config {
>                silent_console = <0>;
>         };
> @@ -150,11 +154,20 @@
>         spi {
>                 #address-cells = <1>;
>                 #size-cells = <0>;
> -               compatible = "intel,ich9";
> +               compatible = "intel,ich-spi";
>                 spi-flash at 0 {
> +                       #size-cells = <1>;
> +                       #address-cells = <1>;
>                         reg = <0>;
>                         compatible = "winbond,w25q64", "spi-flash";
>                         memory-map = <0xff800000 0x00800000>;
> +                       rw-mrc-cache {
> +                               label = "rw-mrc-cache";
> +                               /* Alignment: 4k (for updating) */
> +                               reg = <0x003e0000 0x00010000>;
> +                               type = "wiped";
> +                               wipe-value = [ff];
> +                       };
>                 };
>         };
>
> diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
> new file mode 100644

Looks that you created link.dts again? Guess you may not rebase to
u-boot-x86/next branch correctly?

[snip]

Regards,
Bin