[U-Boot] [PATCH 15/22] ppc4xx: remove WUH405 board
Matthias Fuchs
matthias.fuchs at esd.eu
Mon Jan 12 22:47:28 CET 2015
Signed-off-by: Matthias Fuchs <matthias.fuchs at esd.eu>
---
arch/powerpc/cpu/ppc4xx/Kconfig | 4 -
board/esd/wuh405/Kconfig | 12 -
board/esd/wuh405/MAINTAINERS | 6 -
board/esd/wuh405/Makefile | 10 -
board/esd/wuh405/flash.c | 85 -
board/esd/wuh405/fpgadata.c | 3636 ---------------------------------------
board/esd/wuh405/wuh405.c | 171 --
configs/WUH405_defconfig | 3 -
doc/README.scrapyard | 1 +
include/configs/WUH405.h | 346 ----
10 files changed, 1 insertion(+), 4273 deletions(-)
delete mode 100644 board/esd/wuh405/Kconfig
delete mode 100644 board/esd/wuh405/MAINTAINERS
delete mode 100644 board/esd/wuh405/Makefile
delete mode 100644 board/esd/wuh405/flash.c
delete mode 100644 board/esd/wuh405/fpgadata.c
delete mode 100644 board/esd/wuh405/wuh405.c
delete mode 100644 configs/WUH405_defconfig
delete mode 100644 include/configs/WUH405.h
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 9884894..6c4759a 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -137,9 +137,6 @@ config TARGET_PMC440
config TARGET_VOM405
bool "Support VOM405"
-config TARGET_WUH405
- bool "Support WUH405"
-
config TARGET_DLVISION_10G
bool "Support dlvision-10g"
@@ -221,7 +218,6 @@ source "board/esd/plu405/Kconfig"
source "board/esd/pmc405de/Kconfig"
source "board/esd/pmc440/Kconfig"
source "board/esd/vom405/Kconfig"
-source "board/esd/wuh405/Kconfig"
source "board/g2000/Kconfig"
source "board/gdsys/405ep/Kconfig"
source "board/gdsys/405ex/Kconfig"
diff --git a/board/esd/wuh405/Kconfig b/board/esd/wuh405/Kconfig
deleted file mode 100644
index 8a7df4d..0000000
--- a/board/esd/wuh405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_WUH405
-
-config SYS_BOARD
- default "wuh405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "WUH405"
-
-endif
diff --git a/board/esd/wuh405/MAINTAINERS b/board/esd/wuh405/MAINTAINERS
deleted file mode 100644
index 782c72a..0000000
--- a/board/esd/wuh405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-WUH405 BOARD
-M: Matthias Fuchs <matthias.fuchs at esd-electronics.com>
-S: Maintained
-F: board/esd/wuh405/
-F: include/configs/WUH405.h
-F: configs/WUH405_defconfig
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
deleted file mode 100644
index b9beeff..0000000
--- a/board/esd/wuh405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = wuh405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
deleted file mode 100644
index 23e8164..0000000
--- a/board/esd/wuh405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese at esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/wuh405/fpgadata.c b/board/esd/wuh405/fpgadata.c
deleted file mode 100644
index a964f9f..0000000
--- a/board/esd/wuh405/fpgadata.c
+++ /dev/null
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-0x54, 0xfb, 0x77, 0x1f, 0x28, 0x6c, 0xcc, 0x7f,
-0x63, 0xf3, 0xea, 0xd9, 0x41, 0xf1, 0xc1, 0x5f,
-0xe3, 0x07, 0xd1, 0xfc, 0xa5, 0xed, 0x4e, 0xf9,
-0xc9, 0x56, 0xb7, 0x2b, 0xcd, 0xdf, 0xbe, 0xbf,
-0x2b, 0xa0, 0xec, 0x0c, 0x5b, 0xb2, 0x7a, 0x5b,
-0x93, 0xb5, 0xae, 0x99, 0xcc, 0x12, 0xbc, 0x49,
-0x5b, 0x56, 0x40, 0xb6, 0xd0, 0xe4, 0x4a, 0x0c,
-0x8d, 0xdf, 0x4b, 0x89, 0x3a, 0x9e, 0x38, 0xff,
-0x05, 0x1f, 0xba, 0x20, 0xb0, 0x50, 0x80, 0xa2,
-0x7d, 0x57, 0x24, 0x6a, 0x34, 0x98, 0xa8, 0x4f,
-0xc8, 0x16, 0x43, 0xed, 0x1f, 0x23, 0x81, 0xc8,
-0xcf, 0x2e, 0x34, 0xf9, 0x70, 0x95, 0x78, 0x20,
-0x8d, 0xe4, 0xc3, 0xa0, 0x75, 0x77, 0x7e, 0x46,
-0xe6, 0x11, 0x90, 0x16, 0x2b, 0x21, 0xb6, 0xc9,
-0xfd, 0xb0, 0xc4, 0x43, 0x6c, 0x73, 0x11, 0xe4,
-0xce, 0x72, 0xc1, 0x6f, 0x27, 0xd4, 0xfe, 0x66,
-0xee, 0x62, 0x32, 0xc5, 0xb3, 0x06, 0xcc, 0x4d,
-0xbf, 0x0c, 0x1d, 0xe5, 0x3d, 0xe1, 0xc4, 0xe8,
-0xe0, 0x47, 0x9b, 0xa6, 0xc7, 0x56, 0xe3, 0x01,
-0x08, 0xea, 0x7c, 0x88, 0xd4, 0xe5, 0x5a, 0x2a,
-0x1f, 0x2a, 0x26, 0x52, 0x12, 0xb1, 0x10, 0x97,
-0x55, 0x20, 0xd6, 0x97, 0xfc, 0x5a, 0xa3, 0x55,
-0xa1, 0xbd, 0x04, 0xf9, 0x30, 0xb0, 0x16, 0xe9,
-0x41, 0x92, 0xe4, 0xc3, 0xc5, 0x5d, 0xcf, 0xac,
-0x0e, 0xd1, 0xb1, 0xd2, 0x97, 0xab, 0xf9, 0x0f,
-0xec, 0x3e, 0x7a, 0xba, 0xdc, 0x7a, 0x93, 0xfe,
-0xd2, 0xee, 0x82, 0xb1, 0x52, 0x6b, 0x35, 0xf7,
-0x81, 0xfd, 0x75, 0x2a, 0xcd, 0x9c, 0xf2, 0x76,
-0xdc, 0xac, 0xb5, 0x40, 0x1b, 0x38, 0x0f, 0x8c,
-0x8a, 0x24, 0x1d, 0xa7, 0x06, 0xbf, 0x92, 0xbb,
-0x8d, 0x53, 0x33, 0xfc, 0xc8, 0xb0, 0xe8, 0x03,
-0x35, 0x8a, 0xc9, 0x17, 0x2f, 0x60, 0x02, 0xde,
-0x01, 0x59, 0xec, 0x31, 0x1c, 0xa4, 0x00, 0xeb,
-0x3c, 0x6a, 0x92, 0xb0, 0xcc, 0xa5, 0xc8, 0x8c,
-0x7e, 0x74, 0x7e, 0xf1, 0xf8, 0x8e, 0x5b, 0x1e,
-0x16, 0xeb, 0x22, 0x71, 0x58, 0xf2, 0x81, 0x1b,
-0x35, 0xc5, 0x93, 0xbb, 0x39, 0xab, 0x8b, 0x9a,
-0xa5, 0x18, 0x1e, 0xda, 0xd5, 0xbf, 0x3e, 0xec,
-0x32, 0xd1, 0xbb, 0x98, 0xf1, 0x6d, 0x9e, 0x68,
-0x80, 0x09, 0x0d, 0x4d, 0x3b, 0x6f, 0xf6, 0xb7,
-0x08, 0x8b, 0x05, 0xe2, 0x8b, 0x32, 0x82, 0xcc,
-0x84, 0xc1, 0xd1, 0xbb, 0x0f, 0xd3, 0xa2, 0x45,
-0xfc, 0xea, 0xf1, 0x34, 0xdc, 0x80, 0x83, 0x1e,
-0x89, 0x9e, 0x28, 0xb0, 0x3a, 0x1f, 0x66, 0x0b,
-0xb8, 0xdf, 0x49, 0x50, 0x2c, 0xe0, 0xb6, 0xe8,
-0xff, 0x58, 0x80, 0x62, 0x65, 0xb5, 0x47, 0x1e,
-0x32, 0x2b, 0xb5, 0xe6, 0xef, 0x43, 0x32, 0xf8,
-0x77, 0x3e, 0xe4, 0xac, 0x81, 0x85, 0x4d, 0xd3,
-0xfc, 0x7b, 0x11, 0x0c, 0xd3, 0xa3, 0x2f, 0x21,
-0xcd, 0x9a, 0xad, 0x1b, 0xf8, 0x90, 0xd6, 0xcd,
-0x6a, 0xd8, 0x92, 0xb2, 0x6a, 0x56, 0x14, 0x0f,
-0x13, 0xfc, 0xe6, 0x8d, 0xe0, 0x4d, 0x17, 0x06,
-0x90, 0xdf, 0x7e, 0x28, 0x2e, 0xd3, 0x93, 0xd7,
-0xcb, 0xf0, 0xd0, 0x04, 0xb5, 0x79, 0x14, 0x0f,
-0xf9, 0x2c, 0x3e, 0xf4, 0x9f, 0x69, 0xa9, 0x35,
-0x2b, 0xda, 0x22, 0x19, 0x0e, 0xcf, 0x2f, 0x78,
-0x38, 0x34, 0xb6, 0xb8, 0xf0, 0xba, 0x11, 0x2d,
-0xb8, 0xbf, 0x47, 0xf3, 0x53, 0xc4, 0x53, 0x24,
-0x0e, 0xe4, 0xd1, 0xd7, 0x8d, 0x8d, 0x37, 0xb5,
-0x6e, 0x1a, 0x87, 0x86, 0x9b, 0xfb, 0x69, 0x01,
-0x07, 0x3c, 0xc3, 0x9d, 0xc0, 0x70, 0x89, 0x58,
-0x17, 0x56, 0x40, 0x85, 0xc9, 0x3c, 0x63, 0xa2,
-0xe9, 0x53, 0x00, 0x31, 0xf3, 0x4d, 0x9c, 0x05,
-0x8e, 0x88, 0x96, 0xd5, 0x6b, 0xa5, 0x72, 0xc3,
-0x84, 0x2d, 0xa0, 0xc4, 0x33, 0x85, 0x34, 0x58,
-0x0e, 0x3a, 0x4f, 0xb9, 0x53, 0x08, 0x8a, 0x7f,
-0x0a, 0xd2, 0xae, 0xd1, 0x00, 0xc5, 0x54, 0x93,
-0x18, 0x15, 0x5e, 0x25, 0x82, 0xdf, 0x3a, 0x82,
-0xa3, 0x96, 0xb3, 0x26, 0xcd, 0x9b, 0x56, 0xfb,
-0x5a, 0xe2, 0xbb, 0x04, 0x5b, 0x8a, 0xce, 0x3a,
-0x96, 0x96, 0x1d, 0xec, 0xe8, 0xa9, 0x43, 0xca,
-0xf5, 0x92, 0x84, 0x73, 0x81, 0x77, 0x04, 0xbd,
-0x2e, 0x59, 0x8b, 0x5d, 0xe0, 0x4b, 0x68, 0x92,
-0x6b, 0x20, 0x4c, 0x1b, 0x9a, 0xd8, 0x85, 0x92,
-0x68, 0x51, 0xf2, 0x49, 0x31, 0x3f, 0x22, 0xe9,
-0xf1, 0x0d, 0xd7, 0x8c, 0xf8, 0x90, 0x0e, 0x94,
-0xcf, 0x04, 0x6d, 0xa7, 0xd2, 0x0f, 0xc9, 0x85,
-0x2b, 0x02, 0x1d, 0xed, 0xd5, 0x66, 0x3c, 0x0c,
-0xa1, 0x57, 0xa6, 0x1d, 0xe4, 0x73, 0x34, 0xa3,
-0x21, 0x16, 0xce, 0xf0, 0xdd, 0x15, 0xab, 0x12,
-0x0f, 0xce, 0x64, 0x4c, 0x32, 0x41, 0x62, 0x11,
-0x6e, 0xa1, 0xf9, 0x4a, 0x80, 0x69, 0xe7, 0x1d,
-0x2a, 0x5b, 0xd0, 0x84, 0x87, 0x5c, 0x75, 0x3f,
-0xcd, 0x07, 0x70, 0x89, 0xec, 0x87, 0xec, 0x2c,
-0x3c, 0x2a, 0x1f, 0x21, 0x07, 0x20, 0xcb, 0xed,
-0x47, 0xf4, 0x12, 0x9a, 0xa3, 0x68, 0x7a, 0x2e,
-0x81, 0x34, 0x11, 0x1f, 0x32, 0x32, 0x01, 0xde,
-0x32, 0xf2, 0x21, 0xc6, 0xc3, 0x3d, 0xde, 0xee,
-0xc7, 0x10, 0x0b, 0xf9, 0xb4, 0xc0, 0xc2, 0x02,
-0x99, 0xe7, 0x41, 0x68, 0xb8, 0x12, 0x0f, 0xce,
-0xb7, 0x9b, 0x72, 0xfe, 0xfc, 0xa4, 0x8c, 0x34,
-0x58, 0xc5, 0x32, 0x6a, 0xb6, 0xdc, 0xe0, 0xc3,
-0xb2, 0x98, 0x6f, 0x82, 0x0f, 0xd5, 0xf5, 0x45,
-0x20, 0xe3, 0xb4, 0x86, 0xf3, 0xa7, 0x64, 0x79,
-0x79, 0x13, 0x59, 0x8a, 0xa1, 0xc9, 0xa1, 0xa1,
-0xa1, 0xc9, 0x44, 0x3c, 0xc6, 0x18, 0x96, 0x94,
-0xf7, 0x1d, 0xdf, 0x30, 0x61, 0x2f, 0xae, 0x23,
-0xa7, 0x4a, 0x52, 0x24, 0xeb, 0x15, 0x6b, 0xd8,
-0x82, 0x06, 0xea, 0x86, 0x91, 0x28, 0x1e, 0x93,
-0xfa, 0xb6, 0xe4, 0x43, 0xce, 0xba, 0x30, 0xdb,
-0xc4, 0x91, 0x0f, 0x59, 0x1d, 0x0b, 0x9b, 0x06,
-0x94, 0xf5, 0x35, 0xec, 0xb5, 0x96, 0x78, 0xd5,
-0x33, 0x17, 0x63, 0x5d, 0x48, 0x83, 0x58, 0x62,
-0x0b, 0x3e, 0x9c, 0x43, 0x12, 0xdb, 0x3b, 0x87,
-0x09, 0xa3, 0x22, 0xf8, 0x70, 0x0e, 0x94, 0xf5,
-0xc5, 0xae, 0xca, 0x24, 0x83, 0x39, 0xb7, 0xec,
-0x49, 0x53, 0xc2, 0xfc, 0x63, 0xbb, 0xf0, 0x6d,
-0x62, 0xf3, 0x3f, 0x04, 0x16, 0xa2, 0x4e, 0xac,
-0x9d, 0x37, 0xd7, 0x17, 0xf6, 0xe7, 0xd3, 0xd0,
-0x0e, 0x89, 0x8c, 0x59, 0xe1, 0x01, 0xdc, 0x88,
-0x63, 0x46, 0xae, 0xc0, 0x4c, 0x1f, 0xe6, 0x9f,
-0x18, 0xa9, 0xac, 0x61, 0x8e, 0x46, 0x53, 0x52,
-0xd7, 0x57, 0xc0, 0x8e, 0xc0, 0x7e, 0x88, 0xcf,
-0xd6, 0xaa, 0xfc, 0x08, 0xd9, 0x4f, 0xb2, 0xbc,
-0xf2, 0x88, 0x9e, 0x6f, 0x11, 0x77, 0x90, 0x3f,
-0x9a, 0x3e, 0x92, 0xdc, 0x1f, 0xc7, 0x3b, 0xc8,
-0x9b, 0xe3, 0x53, 0xc4, 0xf2, 0xfb, 0x9b, 0xc1,
-0xfe, 0x53, 0xf1, 0x05, 0xf8, 0x05, 0xf8, 0x2c,
-0x65, 0xc5, 0x29, 0x7c, 0x88, 0xb9, 0x53, 0x9a,
-0x95, 0x46, 0x8b, 0x7a, 0xbf, 0x28, 0x0c, 0xb0,
-0x96, 0x62, 0x7c, 0xa2, 0xb2, 0xc0, 0xfb, 0x59,
-0x4b, 0x26, 0xee, 0xc0, 0x3d, 0xda, 0x5f, 0x48,
-0x15, 0x43, 0xc3, 0x52, 0x13, 0x71, 0xc7, 0x5a,
-0x25, 0x56, 0x33, 0x9e, 0x2c, 0x0d, 0x56, 0x5c,
-0x7f, 0xc4, 0x85, 0x1f, 0x95, 0x99, 0x30, 0xa6,
-0x7d, 0x2d, 0x6c, 0x49, 0xd9, 0xd7, 0x21, 0x58,
-0x29, 0x08, 0xc3, 0x2d, 0x65, 0x7c, 0xa0, 0x1b,
-0xb3, 0xb4, 0xfa, 0xf2, 0xe4, 0xee, 0x67, 0xbc,
-0xd7, 0x8a, 0xd6, 0x57, 0xa1, 0xc1, 0x87, 0x3c,
-0x77, 0x4e, 0x98, 0x4e, 0xeb, 0x63, 0xe4, 0x43,
-0x4b, 0x60, 0xe1, 0x22, 0x9c, 0xb3, 0xcd, 0x90,
-0x0f, 0x9b, 0xe3, 0x99, 0x67, 0xb9, 0xd7, 0xed,
-0xb4, 0x93, 0xcf, 0xf3, 0x13, 0xd3, 0x45, 0xdb,
-0x31, 0xf2, 0xc4, 0x62, 0x0c, 0xd3, 0x8e, 0x81,
-0xf9, 0x27, 0x07, 0xd8, 0x42, 0xf3, 0x40, 0xa2,
-0xf5, 0x8e, 0xf3, 0x21, 0xac, 0x8c, 0xbb, 0x64,
-0xe6, 0xb3, 0x66, 0x0d, 0x39, 0x37, 0x41, 0x14,
-0x31, 0xc4, 0xac, 0xd7, 0x0b, 0x25, 0x88, 0x78,
-0x5e, 0xf0, 0x21, 0x87, 0x2a, 0x43, 0x1a, 0xa4,
-0xb1, 0x32, 0x43, 0x50, 0xa4, 0x2a, 0x28, 0x86,
-0x26, 0xea, 0xcd, 0xf2, 0xaf, 0x91, 0x49, 0x46,
-0x1f, 0x9c, 0x7d, 0xc5, 0x6d, 0x49, 0xb4, 0xb1,
-0xf5, 0x07, 0x9d, 0x87, 0x53, 0x2d, 0xf1, 0x49,
-0x34, 0x03, 0x87, 0x8d, 0xd7, 0xea, 0x46, 0xc9,
-0x3f, 0x78, 0xbd, 0x3d, 0x17, 0x33, 0x4b, 0xc8,
-0x87, 0xef, 0xfe, 0xbe, 0x47, 0xec, 0xfe, 0x7b,
-0xbc, 0x74, 0x2d, 0x31, 0x23, 0x79, 0xa0, 0xbd,
-0x01, 0x06, 0x4a, 0xfe, 0x01, 0xf8, 0xda, 0x5b,
-0x23, 0x0f, 0xdf, 0xbd, 0xbd, 0xfc, 0x9d, 0x1b,
-0x2f, 0xbe, 0x35, 0x26, 0xf8, 0xf0, 0xfd, 0x3a,
-0x1f, 0x2e, 0x47, 0x7c, 0xb8, 0xeb, 0x19, 0xf7,
-0x50, 0xc4, 0x87, 0xc7, 0x05, 0x1f, 0xee, 0xd4,
-0xf9, 0xf0, 0x69, 0xc4, 0x87, 0xbb, 0x78, 0xec,
-0xf3, 0xea, 0xab, 0x02, 0x0b, 0xff, 0x5a, 0xd9,
-0xd9, 0x1e, 0xda, 0xaa, 0x83, 0x22, 0x12, 0xe3,
-0x73, 0xf8, 0x50, 0xfe, 0xf4, 0xbf, 0x6f, 0x62,
-0xff, 0x4f, 0x1b, 0xa0, 0x78, 0xf9, 0x79, 0x7c,
-0x38, 0xd8, 0xe0, 0xc3, 0xee, 0x03, 0xe3, 0x1b,
-0xf3, 0xfd, 0x9b, 0x4f, 0x1e, 0x0f, 0x5d, 0x7a,
-0xa6, 0xff, 0xe3, 0x2f, 0x1e, 0xbd, 0x0f, 0x1e,
-0x11, 0x2f, 0x28, 0x7c, 0xc8, 0xa6, 0xbe, 0xf8,
-0x59, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4, 0xb4,
-0xb4, 0xb4, 0xb4, 0xb4, 0xfe, 0xdf, 0x25, 0x6b,
-0x07, 0xaa, 0x6b, 0x07, 0x2d, 0x2d, 0x2d, 0x2d,
-0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0x2d, 0xad, 0xe7,
-0x4b, 0xd6, 0x0e, 0x09, 0x5d, 0x3b, 0x68, 0x69,
-0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69, 0x69,
-0x69, 0x3d, 0x5f, 0xb2, 0x76, 0x30, 0x65, 0xed,
-0xf0, 0xbf, 0x0e, 0x45, 0x4b, 0x4b, 0x4b, 0x4b,
-0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0x4b, 0xeb, 0xbf,
-0x28, 0x5f, 0xfc, 0xd1, 0x24, 0xf8, 0xe7, 0x79,
-0x1f, 0xb8, 0xf8, 0xce, 0x53, 0xdc, 0x07, 0xf6,
-0xb9, 0xdf, 0x27, 0xd4, 0x3f, 0x6b, 0xf8, 0x50,
-0x25, 0xd1, 0x39, 0x1f, 0x9f, 0x7e, 0xb6, 0xdf,
-0xbf, 0x00, 0x34, 0x34, 0xbf, 0x69, 0xee, 0x33,
-0x01, 0x00,
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
deleted file mode 100644
index 71d16e4..0000000
--- a/board/esd/wuh405/wuh405.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese at esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <malloc.h>
-
-/* ------------------------------------------------------------------------- */
-
-#if 0
-#define FPGA_DEBUG
-#endif
-
-/* fpga configuration data - gzip compressed and generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-
-/*
- * include common fpga code (for esd boards)
- */
-#include "../common/fpga.c"
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-int misc_init_r (void)
-{
- unsigned char *dst;
- ulong len = sizeof(fpgadata);
- int status;
- int index;
- int i;
-
- dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
- if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
- printf ("GUNZIP ERROR - must RESET board to recover\n");
- do_reset (NULL, 0, 0, NULL);
- }
-
- status = fpga_boot(dst, len);
- if (status != 0) {
- printf("\nFPGA: Booting failed ");
- switch (status) {
- case ERROR_FPGA_PRG_INIT_LOW:
- printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_INIT_HIGH:
- printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
- break;
- case ERROR_FPGA_PRG_DONE:
- printf("(Timeout: DONE not high after programming FPGA)\n ");
- break;
- }
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("FPGA: %s\n", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
- /* delayed reboot */
- for (i=20; i>0; i--) {
- printf("Rebooting in %2d seconds \r",i);
- for (index=0;index<1000;index++)
- udelay(1000);
- }
- putc ('\n');
- do_reset(NULL, 0, 0, NULL);
- }
-
- puts("FPGA: ");
-
- /* display infos on fpgaimage */
- index = 15;
- for (i=0; i<4; i++) {
- len = dst[index];
- printf("%s ", &(dst[index+1]));
- index += len+3;
- }
- putc ('\n');
-
- free(dst);
-
- /*
- * Reset FPGA via FPGA_DATA pin
- */
- SET_FPGA(FPGA_PRG | FPGA_CLK);
- udelay(1000); /* wait 1ms */
- SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
- udelay(1000); /* wait 1ms */
-
- /*
- * Reset external DUARTs
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
- udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
- udelay(1000); /* wait 1ms */
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)(DUART0_BA + 4), 0x08);
- out_8((void *)(DUART1_BA + 4), 0x08);
- out_8((void *)(DUART2_BA + 4), 0x08);
- out_8((void *)(DUART3_BA + 4), 0x08);
-
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming WUH405");
- } else {
- puts(str);
- }
-
- putc ('\n');
-
- return 0;
-}
diff --git a/configs/WUH405_defconfig b/configs/WUH405_defconfig
deleted file mode 100644
index dadea20..0000000
--- a/configs/WUH405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_WUH405=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index dfab3d5..a385bde 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+WUH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs at esd.eu>
VOH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs at esd.eu>
PMC405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs at esd.eu>
PCI405 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs at esd.eu>
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
deleted file mode 100644
index e4f0d19..0000000
--- a/include/configs/WUH405.h
+++ /dev/null
@@ -1,346 +0,0 @@
-/*
- * (C) Copyright 2004
- * Stefan Roese, esd gmbh germany, stefan.roese at esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_IDENT_STRING " $Name: $"
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_WUH405 1 /* ...on a WUH405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33333300 /* external frequency to pll */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 2 /* Use UART1 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
-#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
-
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define DUART0_BA 0xF0000400 /* DUART Base Address */
-#define DUART1_BA 0xF0000408 /* DUART Base Address */
-#define DUART2_BA 0xF0000410 /* DUART Base Address */
-#define DUART3_BA 0xF0000418 /* DUART Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
--
1.7.9.5
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