[U-Boot] [PATCHv1 07/22] arm: socfpga: spl: enable sdram, timer and uart

[dinguyen at opensource.altera.com]

From: Dinh Nguyen <dinguyen at opensource.altera.com>

Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>
---
 arch/arm/cpu/armv7/socfpga/spl.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index bd9f338..b123336 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -145,6 +145,10 @@ void spl_board_init(void)
 	/* freeze all IO banks */
 	sys_mgr_frzctrl_freeze_req();
 
+	socfpga_sdram_enable();
+	socfpga_uart0_enable();
+	socfpga_osc1timer_enable();
+
 	debug("Reconfigure Clock Manager\n");
 	/* reconfigure the PLLs */
 	cm_basic_init(&cm_default_cfg);
-- 
2.2.1