[U-Boot] [PATCHv1 13/22] arm: socfpga: spl: Add s_init

[Marek Vasut]

On Wednesday, January 14, 2015 at 05:40:53 PM, dinguyen at opensource.altera.com 
wrote:
> From: Dinh Nguyen <dinguyen at opensource.altera.com>
> 
> s_init will map SDRAM to 0x0.
> 
> Signed-off-by: Dinh Nguyen <dinguyen at opensource.altera.com>

Hi!

[...]

> +void s_init(void)
> +{
> +#ifdef CONFIG_SPL_BUILD
> +	struct socfpga_system_manager *sysmgr_regs =
> +		(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
> +	unsigned long reg;
> +	/*
> +	 * First C code to run. Clear fake OCRAM ECC first as SBE
> +	 * and DBE might triggered during power on
> +	 */
> +	reg = readl(&sysmgr_regs->eccgrp_ocram);
> +	if (reg & SYSMGR_ECC_OCRAM_SERR)
> +		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
> +			&sysmgr_regs->eccgrp_ocram);
> +	if (reg & SYSMGR_ECC_OCRAM_DERR)
> +		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
> +			&sysmgr_regs->eccgrp_ocram);
> +#else
> +	/*
> +	 * Private components security
> +	 * U-Boot : configure private timer, global timer and cpu
> +	 * component access as non secure for kernel stage (as required
> +	 * by kernel)
> +	 */
> +	setbits_le32(SOCFPGA_SCU_SNSAC, 0xfff);

We do this in socfpga/misc.c in arch_early_init_r() already. You should
consolidate this code so we don't have it twice I think.

> +
> +#endif	/* CONFIG_SPL_BUILD */
> +
> +	/* Configure the L2 controller to make SDRAM start at 0	*/
> +	writel(0x1, (SOCFPGA_MPUL2_ADDRESS + SOCFPGA_MPUL2_ADRFLTR_START));

This as well.

> +}
> diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h
> b/arch/arm/include/asm/arch-socfpga/system_manager.h index
> 51d9815..10659f7 100644
> --- a/arch/arm/include/asm/arch-socfpga/system_manager.h
> +++ b/arch/arm/include/asm/arch-socfpga/system_manager.h
> @@ -144,4 +144,14 @@ struct socfpga_system_manager {
>  #define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB			2
>  #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK			0x3
> 
> +/*
> + * SCU Non-secure Access Control
> + */
> +#define SOCFPGA_SCU_SNSAC	(SOCFPGA_MPUSCU_ADDRESS + 0x54)
> +/*
> + * L2 PL-310
> + * for configuring L2 address filtering start address in assembly.
> + */
> +#define SOCFPGA_MPUL2_ADRFLTR_START			(0xC00)

I think this is not needed if you use the code from misc.c , since these
registers are already defined there.

>  #endif /* _SYSTEM_MANAGER_H_ */