[U-Boot] [PATCH v2] powerpc/t1040qds: Add support of SD boot for T1040QDS Board
York Sun
yorksun at freescale.com
Thu Jan 15 20:11:42 CET 2015
Vijay,
On 12/19/2014 04:35 AM, Vijay Rai wrote:
> Add support of 2 stage SD boot loader using SPL framework.
> here, PBL initialise the internal SRAM and copy SPL(160KB). This further
> initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR.
> Finally SPL transer control to u-boot.
>
> Initialise/create followings required for SPL framework
> - Add spl.c which defines board_init_f, board_init_r
> - Update tlb and ddr accordingly
>
> Add T1040QDS_SDCARD_defconfig
> Update t1040_pbi.cfg to support errata A-007662, A-008007 and LAW for CPC1
>
> Signed-off-by: Vijay Rai <vijay.rai at freescale.com>
> ---
> changes from v1:
> -Updated Kconfig to support SPL option for T1040QDS
>
> arch/powerpc/cpu/mpc85xx/Kconfig | 1 +
> board/freescale/t1040qds/MAINTAINERS | 5 ++
> board/freescale/t1040qds/Makefile | 10 ++-
> board/freescale/t1040qds/ddr.c | 5 +-
> board/freescale/t1040qds/spl.c | 155 ++++++++++++++++++++++++++++++++
> board/freescale/t1040qds/t1040_pbi.cfg | 16 +++-
> board/freescale/t1040qds/t1040qds.c | 6 +-
> board/freescale/t1040qds/tlb.c | 11 +++
> configs/T1040QDS_SDCARD_defconfig | 5 ++
> include/configs/T1040QDS.h | 79 +++++++++++++---
> 10 files changed, 273 insertions(+), 20 deletions(-)
> create mode 100644 board/freescale/t1040qds/spl.c
> create mode 100644 configs/T1040QDS_SDCARD_defconfig
>
<snip>
> diff --git a/board/freescale/t1040qds/spl.c b/board/freescale/t1040qds/spl.c
> new file mode 100644
> index 0000000..b601c95
> --- /dev/null
> +++ b/board/freescale/t1040qds/spl.c
> @@ -0,0 +1,155 @@
> +/* Copyright 2013 Freescale Semiconductor, Inc.
Wrong year.
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <malloc.h>
> +#include <ns16550.h>
> +#include <nand.h>
> +#include <i2c.h>
> +#include <mmc.h>
> +#include <fsl_esdhc.h>
> +#include <spi_flash.h>
> +#include "../common/qixis.h"
> +#include "t1040qds_qixis.h"
> +#include <asm/mpc85xx_gpio.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +phys_size_t get_effective_memsize(void)
> +{
> + return CONFIG_SYS_L3_SIZE;
> +}
> +
> +unsigned long get_board_sys_clk(void)
> +{
> + u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
> +
> + switch (sysclk_conf & 0x0F) {
> + case QIXIS_SYSCLK_64:
> + return 64000000;
> + case QIXIS_SYSCLK_83:
> + return 83333333;
> + case QIXIS_SYSCLK_100:
> + return 100000000;
> + case QIXIS_SYSCLK_125:
> + return 125000000;
> + case QIXIS_SYSCLK_133:
> + return 133333333;
> + case QIXIS_SYSCLK_150:
> + return 150000000;
> + case QIXIS_SYSCLK_160:
> + return 160000000;
> + case QIXIS_SYSCLK_166:
> + return 166666666;
> + }
> + return 66666666;
> +}
> +
> +unsigned long get_board_ddr_clk(void)
> +{
> + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
> +
> + switch ((ddrclk_conf & 0x30) >> 4) {
> + case QIXIS_DDRCLK_100:
> + return 100000000;
> + case QIXIS_DDRCLK_125:
> + return 125000000;
> + case QIXIS_DDRCLK_133:
> + return 133333333;
> + }
> + return 66666666;
> +}
> +
> +#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
> +void board_init_f(ulong bootflag)
> +{
> + u32 plat_ratio, sys_clk, uart_clk;
> +#ifdef CONFIG_SPL_NAND_BOOT
> + u32 porsr1, pinctl;
> +#endif
> + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
> +
> +#ifdef CONFIG_SPL_NAND_BOOT
> + /*
> + * There is T1040 SoC issue where NOR, FPGA are inaccessible during
> + * NAND boot because IFC signals > IFC_AD7 are not enabled.
> + * This workaround changes RCW source to make all signals enabled.
> + */
> + porsr1 = in_be32(&gur->porsr1);
> + pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
> + out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
> +#endif
> +
> + /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
> + memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
> +
> + /* Update GD pointer */
> + gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
> +
> + /* compiler optimization barrier needed for GCC >= 3.4 */
> + __asm__ __volatile__("" : : : "memory");
> +
> + console_init_f();
Please check with deep sleep team to see if you need to silent console for SPL boot.
<snip>
> diff --git a/board/freescale/t1040qds/t1040qds.c b/board/freescale/t1040qds/t1040qds.c
> index 13285be..a086e47 100644
> --- a/board/freescale/t1040qds/t1040qds.c
> +++ b/board/freescale/t1040qds/t1040qds.c
> @@ -279,7 +279,11 @@ void qixis_dump_switch(void)
>
> int board_need_mem_reset(void)
> {
> - return 1;
> +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
> + return 1;
> +#else
> + return 0;
> +#endif
> }
>
The change seems wrong. The original code resets DDR by default. You seem
disabling the reset for NOR boot.
<snip>
> diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h
> index 6b396bb..c0ad90e 100644
> --- a/include/configs/T1040QDS.h
> +++ b/include/configs/T1040QDS.h
> @@ -32,11 +32,46 @@
> #define CONFIG_DISPLAY_BOARDINFO
>
> #ifdef CONFIG_RAMBOOT_PBL
> -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
> -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
> -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
> -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
> +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
> +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t104xrdb/t1040_rcw.cfg
> +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> +#define CONFIG_SPL_ENV_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_FLUSH_IMAGE
> +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_FSL_LAW /* Use common FSL init code */
> +#define CONFIG_SYS_TEXT_BASE 0x30001000
> +#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
> +#define CONFIG_SPL_PAD_TO 0x40000
> +#define CONFIG_SPL_MAX_SIZE 0x28000
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SPL_SKIP_RELOCATE
> +#define CONFIG_SPL_COMMON_INIT_DDR
> +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
> +#define CONFIG_SYS_NO_FLASH
> #endif
> +#define RESET_VECTOR_OFFSET 0x27FFC
> +#define BOOT_PAGE_OFFSET 0x27000
> +
> +#ifdef CONFIG_SDCARD
> +#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
> +#define CONFIG_SPL_MMC_SUPPORT
> +#define CONFIG_SPL_MMC_MINIMAL
> +#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
> +#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
> +#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
> +#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
> +#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
> +#ifndef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_MPC85XX_NO_RESETVEC
> +#endif
> +#define CONFIG_SPL_MMC_BOOT
> +#endif
> +
>
> /* High Level Configuration Options */
> #define CONFIG_BOOKE
> @@ -75,15 +110,12 @@
>
> #define CONFIG_ENV_OVERWRITE
>
> -#ifdef CONFIG_SYS_NO_FLASH
> -#define CONFIG_ENV_IS_NOWHERE
> -#else
> +#ifndef CONFIG_SYS_NO_FLASH
> #define CONFIG_FLASH_CFI_DRIVER
> #define CONFIG_SYS_FLASH_CFI
> #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
> #endif
>
> -#ifndef CONFIG_SYS_NO_FLASH
> #if defined(CONFIG_SPIFLASH)
> #define CONFIG_SYS_EXTRA_ENV_RELOC
> #define CONFIG_ENV_IS_IN_SPI_FLASH
> @@ -99,7 +131,7 @@
> #define CONFIG_ENV_IS_IN_MMC
> #define CONFIG_SYS_MMC_ENV_DEV 0
> #define CONFIG_ENV_SIZE 0x2000
> -#define CONFIG_ENV_OFFSET (512 * 1658)
> +#define CONFIG_ENV_OFFSET (512 * 0x800)
> #elif defined(CONFIG_NAND)
> #define CONFIG_SYS_EXTRA_ENV_RELOC
> #define CONFIG_ENV_IS_IN_NAND
> @@ -152,6 +184,17 @@ unsigned long get_board_ddr_clk(void);
> */
> #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
>
> +#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
> +#define CONFIG_SYS_L3_SIZE 256 << 10
> +#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
> +#ifdef CONFIG_RAMBOOT_PBL
> +#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
> +#endif
> +#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
> +#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
> +#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
> +#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
> +
> #define CONFIG_SYS_DCSRBAR 0xf0000000
> #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
>
> @@ -362,7 +405,11 @@ unsigned long get_board_ddr_clk(void);
> #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
> #endif
>
> -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +#ifdef CONFIG_SPL_BUILD
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
> +#else
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
> +#endif
>
> #if defined(CONFIG_RAMBOOT_PBL)
> #define CONFIG_SYS_RAMBOOT
> @@ -410,7 +457,9 @@ unsigned long get_board_ddr_clk(void);
> #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
> #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
> #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
> +#ifndef CONFIG_SPL_BUILD
> #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
> +#endif
>
> /* Use the HUSH parser */
> #define CONFIG_SYS_HUSH_PARSER
> @@ -634,15 +683,21 @@ unsigned long get_board_ddr_clk(void);
> * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
> */
> #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
> -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
> +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
> #elif defined(CONFIG_NAND)
> #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
> -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
> +#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
> #else
> #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
> #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
> +#endif
> +
> +#if defined(CONFIG_SDCARD)
> +#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
> +#else
> #define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
> #endif
> +
> #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
> #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
> #endif /* CONFIG_NOBQFMAN */
>
Please check carefully the ifdef/endif pairs. You messed up. This won't even
pass compiling. Please test.
York
More information about the U-Boot
mailing list