[U-Boot] [PATCH 6/6] imx:mx6sxsabresd board spl support

[Stefano Babic]

Hi Peng,

series looks ok to me - just a small question:

On 30/12/2014 10:24, Peng Fan wrote:
> Add board level spl support for mx6sxsabresd board.
> 
> Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
> ---
>  board/freescale/mx6sxsabresd/MAINTAINERS    |   1 +
>  board/freescale/mx6sxsabresd/mx6sxsabresd.c | 168 ++++++++++++++++++++++++++++
>  2 files changed, 169 insertions(+)
> 
> diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS
> index f52f300..c0f5d9c 100644
> --- a/board/freescale/mx6sxsabresd/MAINTAINERS
> +++ b/board/freescale/mx6sxsabresd/MAINTAINERS
> @@ -4,3 +4,4 @@ S:	Maintained
>  F:	board/freescale/mx6sxsabresd/
>  F:	include/configs/mx6sxsabresd.h
>  F:	configs/mx6sxsabresd_defconfig
> +F:	configs/mx6sxsabresd_spl_defconfig
> diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> index fd8bc72..74f6d40 100644
> --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
> @@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc)
>  
>  int board_mmc_init(bd_t *bis)
>  {
> +#ifndef CONFIG_SPL_BUILD
>  	int i, ret;
>  
>  	/*
> @@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis)
>  	}
>  
>  	return 0;
> +#else
> +	struct src *src_regs = (struct src *)SRC_BASE_ADDR;
> +	u32 val;
> +	u32 port;
> +
> +	val = readl(&src_regs->sbmr1);
> +
> +	if ((val & 0xc0) != 0x40) {
> +		printf("Not boot from USDHC!\n");
> +		return -EINVAL;
> +	}
> +
> +	port = (val >> 11) & 0x3;
> +	printf("port %d\n", port);
> +	switch (port) {
> +	case 1:
> +		imx_iomux_v3_setup_multiple_pads(
> +			usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
> +		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> +		usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
> +		break;
> +	case 2:
> +		imx_iomux_v3_setup_multiple_pads(
> +			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
> +		gpio_direction_input(USDHC3_CD_GPIO);
> +		gpio_direction_output(USDHC3_PWR_GPIO, 1);
> +		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> +		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
> +		break;
> +	case 3:
> +		imx_iomux_v3_setup_multiple_pads(
> +			usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
> +		gpio_direction_input(USDHC4_CD_GPIO);
> +		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> +		usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
> +		break;
> +	}
> +
> +	gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> +	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> +#endif
>  }
>  
>  int board_init(void)
> @@ -394,3 +436,129 @@ int checkboard(void)
>  
>  	return 0;
>  }
> +
> +#ifdef CONFIG_SPL_BUILD
> +#include <libfdt.h>
> +#include <spl.h>
> +#include <asm/arch/mx6-ddr.h>
> +
> +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
> +	.dram_dqm0 = 0x00000028,
> +	.dram_dqm1 = 0x00000028,
> +	.dram_dqm2 = 0x00000028,
> +	.dram_dqm3 = 0x00000028,
> +	.dram_ras = 0x00000020,
> +	.dram_cas = 0x00000020,
> +	.dram_odt0 = 0x00000020,
> +	.dram_odt1 = 0x00000020,
> +	.dram_sdba2 = 0x00000000,
> +	.dram_sdcke0 = 0x00003000,
> +	.dram_sdcke1 = 0x00003000,
> +	.dram_sdclk_0 = 0x00000030,
> +	.dram_sdqs0 = 0x00000028,
> +	.dram_sdqs1 = 0x00000028,
> +	.dram_sdqs2 = 0x00000028,
> +	.dram_sdqs3 = 0x00000028,
> +	.dram_reset = 0x00000020,
> +};
> +
> +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
> +	.grp_addds = 0x00000020,
> +	.grp_ddrmode_ctl = 0x00020000,
> +	.grp_ddrpke = 0x00000000,
> +	.grp_ddrmode = 0x00020000,
> +	.grp_b0ds = 0x00000028,
> +	.grp_b1ds = 0x00000028,
> +	.grp_ctlds = 0x00000020,
> +	.grp_ddr_type = 0x000c0000,
> +	.grp_b2ds = 0x00000028,
> +	.grp_b3ds = 0x00000028,
> +};
> +
> +const struct mx6_mmdc_calibration mx6_mmcd_calib = {
> +	.p0_mpwldectrl0 = 0x00290025,
> +	.p0_mpwldectrl1 = 0x00220022,
> +	.p0_mpdgctrl0 = 0x41480144,
> +	.p0_mpdgctrl1 = 0x01340130,
> +	.p0_mprddlctl = 0x3C3E4244,
> +	.p0_mpwrdlctl = 0x34363638,
> +};
> +
> +static struct mx6_ddr3_cfg mem_ddr = {
> +	.mem_speed = 1600,
> +	.density = 4,
> +	.width = 32,
> +	.banks = 8,
> +	.rowaddr = 15,
> +	.coladdr = 10,
> +	.pagesz = 2,
> +	.trcd = 1375,
> +	.trcmin = 4875,
> +	.trasmin = 3500,
> +};
> +
> +static void ccgr_init(void)
> +{
> +	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> +
> +	writel(0xFFFFFFFF, &ccm->CCGR0);
> +	writel(0xFFFFFFFF, &ccm->CCGR1);
> +	writel(0xFFFFFFFF, &ccm->CCGR2);
> +	writel(0xFFFFFFFF, &ccm->CCGR3);
> +	writel(0xFFFFFFFF, &ccm->CCGR4);
> +	writel(0xFFFFFFFF, &ccm->CCGR5);
> +	writel(0xFFFFFFFF, &ccm->CCGR6);
> +	writel(0xFFFFFFFF, &ccm->CCGR7);
> +}
> +

Is it ok to enable all clocks ? This is quite uncommon in U-Boot and it
can raise some issues when Linux is booted because it assumes that
clocks are turned off. Anyway, this is only a question: if this is ok
for you (I do not test on this board), it is not an issue.

> +static void spl_dram_init(void)
> +{
> +	struct mx6_ddr_sysinfo sysinfo = {
> +		.dsize = mem_ddr.width/32,
> +		.cs_density = 24,
> +		.ncs = 1,
> +		.cs1_mirror = 0,
> +		.rtt_wr = 2,
> +		.rtt_nom = 2,		/* RTT_Nom = RZQ/2 */
> +		.walat = 1,		/* Write additional latency */
> +		.ralat = 5,		/* Read additional latency */
> +		.mif3_mode = 3,		/* Command prediction working mode */
> +		.bi_on = 1,		/* Bank interleaving enabled */
> +		.sde_to_rst = 0x10,	/* 14 cycles, 200us (JEDEC default) */
> +		.rst_to_cke = 0x23,	/* 33 cycles, 500us (JEDEC default) */
> +	};
> +
> +	mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
> +	mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
> +}
> +
> +void board_init_f(ulong dummy)
> +{
> +	/* setup AIPS and disable watchdog */
> +	arch_cpu_init();
> +
> +	ccgr_init();
> +
> +	/* iomux and setup of i2c */
> +	board_early_init_f();
> +
> +	/* setup GP timer */
> +	timer_init();
> +
> +	/* UART clocks enabled and gd valid - init serial console */
> +	preloader_console_init();
> +
> +	/* DDR initialization */
> +	spl_dram_init();
> +
> +	/* Clear the BSS. */
> +	memset(__bss_start, 0, __bss_end - __bss_start);
> +
> +	/* load/boot image from boot device */
> +	board_init_r(NULL, 0);
> +}
> +
> +void reset_cpu(ulong addr)
> +{
> +}
> +#endif
> 

Best regards,
Stefano Babic

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