[U-Boot] [PATCH v3 0/12] Add support for caching Memory Reference Code data

[Simon Glass]

Since the memory reference code is so slow on x86, add a feature to bypass
this, storing the previous parameters in SPI flash. This saves around 500ms
on each boot.

Also enable a SPI flash environment.

Changes in v3:
- Add new patch to move checksum to its own file in net/
- Adjust net/ code to use the new checksum functions
- Use checksum code that is now in net/checksum.c
- Adjust functions to remain compatible with other RTC drivers
- Drop accidental creation of link.dts due to bad rebase
- Use checksum code from net/checksum.c
- Add misc_init_r() call for link now that it is shared with chromebook_link

Changes in v2:
- Use intel,ich-spi as the compatible string
- Refactor IP checksum patches
- Adjust the mc146818 driver instead of adding a new cmos.h header
- Make changes to chromebook_link.dts since link.dts is gone
- Use intel,ich-spi as the compatible string
- Update for the new CMOS RAM access functions in the RTC
- Add a comment about why both CMOS RAM and SPI flash are used for the cache

Simon Glass (12):
  x86: dts: Add compatible string for Intel ICH9 SPI controller
  net: Add a separate file for IP checksumming
  net: Use new checksum functions
  x86: Use ipchecksum from net/
  x86: rtc: mc146818: Add helpers to read/write CMOS RAM
  x86: spi: Add device tree support
  Allow architecture-specific memory reservation
  x86: dts: Add SPI flash MRC details for chromebook_link
  x86: Implement a cache for Memory Reference Code parameters
  x86: config: Enable hook for saving MRC configuration
  x86: ivybridge: Drop the Kconfig MRC cache information
  x86: config: chromebook_link: Enable environment

 arch/x86/cpu/coreboot/Makefile                  |   1 -
 arch/x86/cpu/coreboot/coreboot.c                |   5 +
 arch/x86/cpu/coreboot/ipchecksum.c              |  55 ------
 arch/x86/cpu/coreboot/tables.c                  |   8 +-
 arch/x86/cpu/ivybridge/Kconfig                  |  28 ---
 arch/x86/cpu/ivybridge/Makefile                 |   1 +
 arch/x86/cpu/ivybridge/mrccache.c               | 156 +++++++++++++++
 arch/x86/cpu/ivybridge/sdram.c                  | 253 ++++++++++++++++++++++++
 arch/x86/dts/chromebook_link.dts                |  15 +-
 arch/x86/include/asm/arch-coreboot/ipchecksum.h |  37 ----
 arch/x86/include/asm/arch-ivybridge/mrccache.h  |  51 +++++
 arch/x86/include/asm/global_data.h              |   3 +
 common/board_f.c                                |   7 +
 drivers/rtc/mc146818.c                          | 121 +++++++-----
 drivers/spi/ich.c                               |   7 +
 include/configs/chromebook_link.h               |   8 +
 include/configs/x86-common.h                    |   1 +
 include/fdtdec.h                                |   1 +
 include/net.h                                   |  32 ++-
 include/rtc.h                                   |  32 +++
 lib/fdtdec.c                                    |   1 +
 net/Makefile                                    |   1 +
 net/checksum.c                                  |  60 ++++++
 net/net.c                                       |  25 +--
 net/ping.c                                      |  10 +-
 25 files changed, 713 insertions(+), 206 deletions(-)
 delete mode 100644 arch/x86/cpu/coreboot/ipchecksum.c
 create mode 100644 arch/x86/cpu/ivybridge/mrccache.c
 delete mode 100644 arch/x86/include/asm/arch-coreboot/ipchecksum.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h
 create mode 100644 net/checksum.c

-- 
2.2.0.rc0.207.ga3a616c