[U-Boot] [PATCH 4/5] Move PLL power-up from power init to memory init

[Marek Vasut]

On Wednesday, January 21, 2015 at 12:55:17 PM, Graeme Russ wrote:
> mxs_power_clock2pll() does not actually switch the CPU clock to the PLL.
> All it does is power-up the PLL and set the CLKCTRL_CLKSEQ_BYPASS_CPU bit
> (which was already set by mxs_power_clock2xtal() anyway)
> 
> spl_mem_init.c sets up the fractional divisor (which is required to run
> the CPU from the PLL) and clears the CLKCTRL_CLKSEQ_BYPASS_CPU bit (which
> switches the CPU clock to the PLL)
> 
> It makes more sense to power-up the PLL in spl_mem_init.c. While moving
> the PLL power-up, we may as well properly configure how the PLL lock is
> started and confirmed
> 
> Signed-off-by: Graeme Russ <gruss at tss-engineering.com>
> ---
> 
>  arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c   | 31 ++++++++++++++++++++
>  arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 45
> ----------------------------- 2 files changed, 31 insertions(+), 45
> deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index a744e5d..af4ed8c 100644
> --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
> @@ -340,10 +340,41 @@ static void mx28_mem_init(void)
>  }
>  #endif
> 
> +/**
> + * mxs_mem_powerup_pll() - Powerup PLL0
> + *
> + * This function turns on power to PLL0. The CPU clock will be switched to
> + * PLL0 after the fractional divider and SDRAM have been configured.
> + */
> +static void mxs_mem_powerup_pll(void)
> +{
> +	struct mxs_clkctrl_regs *clkctrl_regs =
> +		(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
> +
> +	/* Power up PLL0 */
> +	debug("SPL: Powering up PLL0\n");
> +	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
> +		     CLKCTRL_PLL0CTRL0_POWER);
> +
> +	/* Toggle FORCE_LOCK to initiate the PLL lock procedure */
> +	setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl1,
> +		     CLKCTRL_PLL0CTRL1_FORCE_LOCK);

Are you positive that this write really hits the hardware ? You might
want to read the register back before issuing another write to it.

> +	clrbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl1,
> +		     CLKCTRL_PLL0CTRL1_FORCE_LOCK);
> +
> +	/* Wait until the PLL has a stable lock - takes ~50us */
> +	while (!(readl(&clkctrl_regs->hw_clkctrl_pll0ctrl1) &
> +		 CLKCTRL_PLL0CTRL1_LOCK))
> +		;

Use mxs_wait_mask_ here I'd say.
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