[U-Boot] [PATCH v3 08/12] x86: dts: Add SPI flash MRC details for chromebook_link

[Simon Glass]

On 19 January 2015 at 22:16, Simon Glass <sjg at chromium.org> wrote:
> Correct the SPI flash compatible string, add an alias and specify the
> position of the MRC cache, used to store SDRAM training settings for the
> Memory Reference Code.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v3:
> - Drop accidental creation of link.dts due to bad rebase
>
> Changes in v2:
> - Make changes to chromebook_link.dts since link.dts is gone
> - Use intel,ich-spi as the compatible string
>
>  arch/x86/dts/chromebook_link.dts | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)

Applied to u-boot-x86.