[U-Boot] [PATCH v3 09/12] x86: Implement a cache for Memory Reference Code parameters

[Simon Glass]

On 19 January 2015 at 22:16, Simon Glass <sjg at chromium.org> wrote:
> The memory reference code takes a very long time to 'train' its SDRAM
> interface, around half a second. To avoid this delay on every boot we can
> store the parameters from the last training sessions to speed up the next.
>
> Add an implementation of this, storing the training data in CMOS RAM and
> SPI flash.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v3:
> - Use checksum code from net/checksum.c
>
> Changes in v2:
> - Update for the new CMOS RAM access functions in the RTC
> - Add a comment about why both CMOS RAM and SPI flash are used for the cache
>
>  arch/x86/cpu/ivybridge/Makefile                |   1 +
>  arch/x86/cpu/ivybridge/mrccache.c              | 156 +++++++++++++++
>  arch/x86/cpu/ivybridge/sdram.c                 | 253 +++++++++++++++++++++++++
>  arch/x86/include/asm/arch-ivybridge/mrccache.h |  51 +++++
>  arch/x86/include/asm/global_data.h             |   3 +
>  5 files changed, 464 insertions(+)
>  create mode 100644 arch/x86/cpu/ivybridge/mrccache.c
>  create mode 100644 arch/x86/include/asm/arch-ivybridge/mrccache.h

Applied to u-boot-x86.