[U-Boot] [PATCH 0/23] x86: Add bare support for Intel Minnowboard Max

[Bin Meng]

Hi Simon,

On Tue, Jan 27, 2015 at 9:22 AM, Simon Glass <sjg at chromium.org> wrote:
> This series adds support for the Intel Minnowboard Max (called Minnowmax
> for short). Along the way a few refactors and additions are made:
>
> - The Intel Firmware Support Package support is moved from queensbay to a
> common location
> - PCI support for XHCI is added
> - A few tweaks are made to the PCI support
> - Support for the debug UART (early debug output) is provided
> - The microcode tool now also supports reading in header files
>
> This board has been lightly tested. The following seem to work:
>
> - USB2 on the blue port (not USB3), e.g. for keyboard
> - Ethernet
> - HDMI out and console
> - UART
> - uSD card
> - SPI
>
> SATA is detected but I have not attached a drive to try it. USB3 shows signs
> of life but does not detect a USB stick, and crashes when trying to use a
> USB Ethernet adaptor.
>
> For SPI some parts cannot be read and others cannot be written. This seems
> to be a feature of the Intel hardware configuration. It may be possible to
> fix this using the SPI registers but I cannot work out how / lost interest
> trying. So far, addresses from 500000 to 700000 can be used.
>
> I have not tried the ICH GPIO driver but it likely needs work before it will
> function. I2C is not supported as there is currently no U-Boot driver for
> this.
>
> The zboot command can be used to start a bzImage kernel. Verified boot is
> supported - use mkimage to sign images as described in this walk-through:
> doc/uImage.FIT/beaglebone_vboot.txt
>
> Boot time is grim:
> - 1423ms to set up display (Intel FSP)
> - 454ms to scan AHCI (when no devices are connected)
> - ~1000ms to power up and start cache-as-RAM init (Intel FSP)
>      (this is not benchmarked, may be inaccurate)
> - ~950ms to set up memory and initial machine configuration (Intel FSP)
>      (this is not benchmarked, may be inaccurate)
>
> So it takes over 4 seconds to get to booting a kernel.
>
> Implementing the Memory Reference Code (MRC) cache should improve this
> slightly (perhaps a reduction of 500-1000ms). This cache is implemented for
> ivybridge so that code needs to be moved into a generic x86 directory and
> plumbed into the FSP code. This has not been done in this series. Also the
> video and SATA/AHCI can be disabled if preferred.
>
> It is also possible to run as a coreboot payload. See the instructions in
> README.x86 for this. In this case video does not work since coreboot does
> not pass through the VESA display information.
>
> To support the single-core 1GB variant, changes would need to be made to
> arch/x86/cpu/baytrail/fsp_configs.c to select different values for the
> memory. The microcode update may need to change also.
>
> This series is available at u-boot-x86 branch minnow-working.
>

I have finished the review of this patch series. Generally they look
pretty good. Glad to see we have another new Intel board supported
running U-Boot 'bare'!

[snip]

Regards,
Bin