[U-Boot] [RFC PATCH] ARM: Activate hypervisor mode for TI am5726 (OMAP5/dra7)

Frank Bormann frank.bormann at zoho.com
Tue Jan 27 19:56:12 CET 2015


I was wondering if I could have any input on the patch below activating
hypervisor mode on TI OMAP5-based SoC. The patch essentially uses the
on-chip ROM code API to enable hypervisor mode on the primary A15 core
and goes in tandem with a Linux kernel patch recently accepted into
omap-for-v3.19/fixes that checks hypervisor mode on the primary A15 core
and sets it accordingly on additional cores being activated.

I am aware that there is some development going on for ARM's PSCI that
amongst other things is supposed to deal with hypervisor activation in a
more generic fashion and I am wondering if there is any preference on
how to properly activate hypervisor mode for the TI SoCs mentioned above.



u-boot patch:

Enable hypervisor mode for AM5726
  arch/arm/cpu/armv7/omap-common/lowlevel_init.S |   13 +++++++++++++
  1 file changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
index 86c0e42..696da4b 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -19,7 +19,20 @@
  	str	r0, [r1]
+ * Turn on hypervisor mode on CPU#0
+ */
+	mov	r0, lr		@ This is a great place to switch into hyp mode
+				@ only the r0 was needed from _start and is now
+				@ free; all other general purpose registers were
+				@ already free.
+	ldr	r12, =0x102	@ Set PL310 control register - value in R0
+	.word	0xe1600070	@ SMC #0 - hand assembled because -march=armv5
+				@ call ROM Code API to set control register
  	bx	lr


Link to the corresponding Linux kernel patch:


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