[U-Boot] [PATCH 10/10] dt: socfpga: Import and enable Arria V DK DTS

[Marek Vasut]

Import DTS for Arria V development kit and enable support
for DT. The DT is imported from Linux 3.19-rc1 as of commit
97bf6af1f928216fd6c5a66e8a57bfa95a659672 .

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Chin Liang See <clsee at opensource.altera.com>
Cc: Dinh Nguyen <dinguyen at opensource.altera.com>
Acked-by: Pavel Machek <pavel at denx.de>
Reviewed-by: Stefan Roese <sr at denx.de>
Cc: Vince Bridgers <vbridger at opensource.altera.com>
---
 arch/arm/dts/Makefile                 |  1 +
 arch/arm/dts/socfpga_arria5.dtsi      | 34 ++++++++++++++++
 arch/arm/dts/socfpga_arria5_socdk.dts | 74 +++++++++++++++++++++++++++++++++++
 configs/socfpga_arria5_defconfig      |  2 +
 4 files changed, 111 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria5.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria5_socdk.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 22f122f..cbe5b86 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -50,6 +50,7 @@ dtb-$(CONFIG_ZYNQ) += zynq-zc702.dtb \
 dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
 
 dtb-$(CONFIG_SOCFPGA) +=				\
+	socfpga_arria5_socdk.dtb			\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_socrates.dtb
 
diff --git a/arch/arm/dts/socfpga_arria5.dtsi b/arch/arm/dts/socfpga_arria5.dtsi
new file mode 100644
index 0000000..5175f03
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5.dtsi
@@ -0,0 +1,34 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+/* First 4KB has trampoline code for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+#include "socfpga.dtsi"
+
+/ {
+	soc {
+		clkmgr at ffd04000 {
+			clocks {
+				osc1 {
+					clock-frequency = <25000000>;
+				};
+			};
+		};
+
+		mmc0: dwmmc0 at ff704000 {
+			num-slots = <1>;
+			broken-cd;
+			bus-width = <4>;
+			cap-mmc-highspeed;
+			cap-sd-highspeed;
+		};
+
+		sysmgr at ffd08000 {
+			cpu1-start-addr = <0xffd080c4>;
+		};
+	};
+};
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
new file mode 100644
index 0000000..4e529a1
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -0,0 +1,74 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_arria5.dtsi"
+
+/ {
+	model = "Altera SOCFPGA Arria V SoC Development Kit";
+	compatible = "altr,socfpga-arria5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	aliases {
+		/* this allow the ethaddr uboot environmnet variable contents
+		* to be added to the gmac1 device tree blob.
+		*/
+		ethernet0 = &gmac1;
+	};
+
+	regulator_3_3v: 3-3-v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+
+	rxd0-skew-ps = <0>;
+	rxd1-skew-ps = <0>;
+	rxd2-skew-ps = <0>;
+	rxd3-skew-ps = <0>;
+	txen-skew-ps = <0>;
+	txc-skew-ps = <2600>;
+	rxdv-skew-ps = <0>;
+	rxc-skew-ps = <2000>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom at 51 {
+		compatible = "atmel,24c32";
+		reg = <0x51>;
+		pagesize = <32>;
+	};
+
+	rtc at 68 {
+		compatible = "dallas,ds1339";
+		reg = <0x68>;
+	};
+};
+
+&mmc0 {
+	vmmc-supply = <&regulator_3_3v>;
+	vqmmc-supply = <&regulator_3_3v>;
+};
+
+&usb1 {
+	status = "okay";
+};
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index f290042..f152e9d 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -1,3 +1,5 @@
 CONFIG_SPL=y
 +S:CONFIG_ARM=y
 +S:CONFIG_TARGET_SOCFPGA_ARRIA5=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria5_socdk"
-- 
2.1.3