[U-Boot] [PATCH v3 0/8] dm: x86: PCI/SPI fixes for minnowboard MAX
Simon Glass
sjg at chromium.org
Sat Jul 4 02:28:20 CEST 2015
The SPI flash starts off protected on baytrail. The code which is supposed to
fix this is broken. This series fixes that, enables the SPI environment and
adds documentation.
Also when driver model is enabled for PCI some bugs appear. This series fixes
those and enables driver model for PCI on minnowboard MAX.
Changes in v3:
- Correct parameter order with ich_writeb()
- Drop the asm/pci.h header file also
- Drop the patch to board_f.c as it is not needed, and interferes with the fix
- Add a comment about why gd->pci_ram_top is being set
Changes in v2:
- Continue to use writew for ICH7
- Use ich_read/write() for BIOS protection update
- Fix typos in README.x86
- Rename the ops and ids arrays for consistency
- Drop the coreboot PCI driver which is no-longer needed
- Only limit the PCI system memory region on x86 machines
- Use md5sum -b
- Rebase on x86/master
Simon Glass (8):
dm: spi: Correct status register access width
dm: spi: Correct BIOS protection logic for ICH9
dm: spi: Enable environment for minnowmax
x86: Add ROM image description for minnowmax
x86: pci: Tidy up the generic x86 PCI driver
dm: x86: minnowmax: Move PCI to use driver model
dm: x86: baytrail: Correct PCI region 3 when driver model is used
x86: Add binary blob checksums for Minnowboard MAX
arch/x86/cpu/baytrail/Makefile | 1 -
arch/x86/cpu/baytrail/pci.c | 46 ---------------------------------------
arch/x86/cpu/coreboot/pci.c | 22 -------------------
arch/x86/cpu/cpu.c | 2 ++
arch/x86/dts/minnowmax.dts | 10 +++++++++
configs/minnowmax_defconfig | 1 +
doc/README.x86 | 25 +++++++++++++++++++++
drivers/pci/pci-uclass.c | 8 +++++--
drivers/pci/pci_x86.c | 13 ++++++-----
drivers/spi/ich.c | 15 ++++++++-----
include/asm-generic/global_data.h | 1 +
include/configs/minnowmax.h | 6 ++---
12 files changed, 65 insertions(+), 85 deletions(-)
delete mode 100644 arch/x86/cpu/baytrail/pci.c
--
2.4.3.573.g4eafbef
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