[U-Boot] [PATCH 1/3] dm: dts: ls2085a: Bring in ls2085a dts files from linux kernel

[Wang Haikun]

On 6/26/2015 7:53 PM, Haikun Wang wrote:
> From: Haikun Wang <Haikun.Wang at freescale.com>
>
> Bring in required device tree files for ls2085a from Linux.
> These are initially unchanged and have a number of pieces not needed by U-Boot.
Hi Simon,

I got below comment when review this patch internal.
Please help me confirm.

"For new platforms like ARM64, it was discussed to not duplicate the DTS 
in u-boot and Linux, simply because that will break compatibility with 
other bootloaders like Linaro's BootMonitor and UEFI bootloader, which 
do not place the DTS in the bootloader. Also in near future, with DTS 
being replaced by ACPI gradually for ARM64 platforms, it was discussed 
that in a longer run it would be beneficial to move DTS out of both 
u-boot and Linux and maintain it as a separate tree."

Best regards,
Wang Haikun
>
> Signed-off-by: Haikun Wang <Haikun.Wang at freescale.com>
> ---
>   arch/arm/dts/fsl-ls2085a.dtsi | 120 ++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 120 insertions(+)
>   create mode 100644 arch/arm/dts/fsl-ls2085a.dtsi
>
> diff --git a/arch/arm/dts/fsl-ls2085a.dtsi b/arch/arm/dts/fsl-ls2085a.dtsi
> new file mode 100644
> index 0000000..f0679a8
> --- /dev/null
> +++ b/arch/arm/dts/fsl-ls2085a.dtsi
> @@ -0,0 +1,120 @@
> +/*
> + * Freescale ls2085a SOC common device tree source
> + *
> + * Copyright 2013-2015 Freescale Semiconductor, Inc.
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +/ {
> +	compatible = "fsl,ls2085a";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		/*
> +		 * We expect the enable-method for cpu's to be "psci", but this
> +		 * is dependent on the SoC FW, which will fill this in.
> +		 *
> +		 * Currently supported enable-method is psci v0.2
> +		 */
> +
> +		/* We have 4 clusters having 2 Cortex-A57 cores each */
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x0>;
> +		};
> +
> +		cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x1>;
> +		};
> +
> +		cpu at 100 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x100>;
> +		};
> +
> +		cpu at 101 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x101>;
> +		};
> +
> +		cpu at 200 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x200>;
> +		};
> +
> +		cpu at 201 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x201>;
> +		};
> +
> +		cpu at 300 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x300>;
> +		};
> +
> +		cpu at 301 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a57";
> +			reg = <0x0 0x301>;
> +		};
> +	};
> +
> +	memory at 80000000 {
> +		device_type = "memory";
> +		reg = <0x00000000 0x80000000 0 0x80000000>;
> +		      /* DRAM space - 1, size : 2 GB DRAM */
> +	};
> +
> +	gic: interrupt-controller at 6000000 {
> +		compatible = "arm,gic-v3";
> +		reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
> +		      <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		interrupts = <1 9 0x4>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
> +			     <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
> +			     <1 11 0x8>, /* Virtual PPI, active-low */
> +			     <1 10 0x8>; /* Hypervisor PPI, active-low */
> +	};
> +
> +	serial0: serial at 21c0500 {
> +		device_type = "serial";
> +		compatible = "fsl,ns16550", "ns16550a";
> +		reg = <0x0 0x21c0500 0x0 0x100>;
> +		clock-frequency = <0>;	/* Updated by bootloader */
> +		interrupts = <0 32 0x1>; /* edge triggered */
> +	};
> +
> +	serial1: serial at 21c0600 {
> +		device_type = "serial";
> +		compatible = "fsl,ns16550", "ns16550a";
> +		reg = <0x0 0x21c0600 0x0 0x100>;
> +		clock-frequency = <0>; 	/* Updated by bootloader */
> +		interrupts = <0 32 0x1>; /* edge triggered */
> +	};
> +
> +	fsl_mc: fsl-mc at 80c000000 {
> +		compatible = "fsl,qoriq-mc";
> +		reg = <0x00000008 0x0c000000 0 0x40>,	 /* MC portal base */
> +		      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
> +	};
> +};
>