[U-Boot] [PATCH 23/55] dm: power: Add support for the S5M8767 PMIC
Przemyslaw Marczak
p.marczak at samsung.com
Fri Jul 10 13:52:37 CEST 2015
Hello Simon,
On 07/03/2015 02:16 AM, Simon Glass wrote:
> This PMIC is used with SoCs which need a combination of BUCKs and LDOs. The
> driver supports probing and basic register access. It supports the standard
> device tree binding and supports driver model. A regulator driver can be
> provided also.
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> drivers/power/pmic/Kconfig | 9 +++++
> drivers/power/pmic/Makefile | 2 +
> drivers/power/pmic/s5m8767.c | 95 ++++++++++++++++++++++++++++++++++++++++++++
> include/power/s5m8767.h | 85 +++++++++++++++++++++++++++++++++++++++
> 4 files changed, 191 insertions(+)
> create mode 100644 drivers/power/pmic/s5m8767.c
> create mode 100644 include/power/s5m8767.h
>
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index fd8af81..7b98189 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -42,6 +42,15 @@ config DM_PMIC_SANDBOX
>
> Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt
>
> +config PMIC_S5M8767
> + bool "Enable Driver Model for the Samsung S5M8767 PMIC"
> + depends on DM_PMIC
> + ---help---
> + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use
> + as a SoC power controller. It also provides 32KHz clock outputs. This
> + driver provides basic register access and sets up the attached
> + regulators if regulator support is enabled.
> +
> config PMIC_TPS65090
> bool "Enable driver for Texas Instruments TPS65090 PMIC"
> depends on DM_PMIC
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index 2316e3b..ee23c26 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -9,6 +9,8 @@ obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
> obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
> obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
> obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
> +obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
> +
> obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
> obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
> obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
> diff --git a/drivers/power/pmic/s5m8767.c b/drivers/power/pmic/s5m8767.c
> new file mode 100644
> index 0000000..075fe7e
> --- /dev/null
> +++ b/drivers/power/pmic/s5m8767.c
> @@ -0,0 +1,95 @@
> +/*
> + * Copyright (C) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <errno.h>
> +#include <dm.h>
> +#include <i2c.h>
> +#include <power/pmic.h>
> +#include <power/regulator.h>
> +#include <power/s5m8767.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static const struct pmic_child_info pmic_children_info[] = {
> + { .prefix = "LDO", .driver = S5M8767_LDO_DRIVER },
> + { .prefix = "BUCK", .driver = S5M8767_BUCK_DRIVER },
> + { },
> +};
> +
> +static int s5m8767_reg_count(struct udevice *dev)
> +{
> + return S5M8767_NUM_OF_REGS;
> +}
> +
> +static int s5m8767_write(struct udevice *dev, uint reg, const uint8_t *buff,
> + int len)
> +{
> + if (dm_i2c_write(dev, reg, buff, len)) {
> + error("write error to device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int s5m8767_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
> +{
> + if (dm_i2c_read(dev, reg, buff, len)) {
> + error("read error from device: %p register: %#x!", dev, reg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +int s5m8767_enable_32khz_cp(struct udevice *dev)
> +{
> + return pmic_clrsetbits(dev, S5M8767_EN32KHZ_CP, 0, 1 << 1);
> +}
> +
> +static int s5m8767_bind(struct udevice *dev)
> +{
> + int node;
> + const void *blob = gd->fdt_blob;
> + int children;
> +
> + node = fdt_subnode_offset(blob, dev->of_offset, "regulators");
> + if (node <= 0) {
> + debug("%s: %s regulators subnode not found!", __func__,
> + dev->name);
> + return -ENXIO;
> + }
> +
> + debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
> +
> + children = pmic_bind_children(dev, node, pmic_children_info);
> + if (!children)
> + debug("%s: %s - no child found\n", __func__, dev->name);
> +
> + /* Always return success for this device */
> + return 0;
> +}
> +
> +static struct dm_pmic_ops s5m8767_ops = {
> + .reg_count = s5m8767_reg_count,
> + .read = s5m8767_read,
> + .write = s5m8767_write,
> +};
> +
> +static const struct udevice_id s5m8767_ids[] = {
> + { .compatible = "samsung,s5m8767-pmic" },
> + { }
> +};
> +
> +U_BOOT_DRIVER(pmic_s5m8767) = {
> + .name = "s5m8767_pmic",
> + .id = UCLASS_PMIC,
> + .of_match = s5m8767_ids,
> + .bind = s5m8767_bind,
> + .ops = &s5m8767_ops,
> +};
> diff --git a/include/power/s5m8767.h b/include/power/s5m8767.h
> new file mode 100644
> index 0000000..ba88ff7
> --- /dev/null
> +++ b/include/power/s5m8767.h
> @@ -0,0 +1,85 @@
> +/*
> + * Copyright (c) 2015 Google, Inc
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#ifndef __S5M8767_H_
> +#define __S5M8767_H_
> +
> +enum s5m8767_regnum {
> + S5M8767_BUCK1 = 0,
> + S5M8767_BUCK2,
> + S5M8767_BUCK3,
> + S5M8767_BUCK4,
> + S5M8767_BUCK5,
> + S5M8767_BUCK6,
> + S5M8767_BUCK7,
> + S5M8767_BUCK8,
> + S5M8767_BUCK9,
> + S5M8767_LDO1,
> + S5M8767_LDO2,
> + S5M8767_LDO3,
> + S5M8767_LDO4,
> + S5M8767_LDO5,
> + S5M8767_LDO6,
> + S5M8767_LDO7,
> + S5M8767_LDO8,
> + S5M8767_LDO9,
> + S5M8767_LDO10,
> + S5M8767_LDO11,
> + S5M8767_LDO12,
> + S5M8767_LDO13,
> + S5M8767_LDO14,
> + S5M8767_LDO15,
> + S5M8767_LDO16,
> + S5M8767_LDO17,
> + S5M8767_LDO18,
> + S5M8767_LDO19,
> + S5M8767_LDO20,
> + S5M8767_LDO21,
> + S5M8767_LDO22,
> + S5M8767_LDO23,
> + S5M8767_LDO24,
> + S5M8767_LDO25,
> + S5M8767_LDO26,
> + S5M8767_LDO27,
> + S5M8767_LDO28,
> + S5M8767_EN32KHZ_CP,
> +
> + S5M8767_NUM_OF_REGS,
> +};
> +
> +struct sec_voltage_desc {
> + int max;
> + int min;
> + int step;
> +};
> +
> +/**
> + * struct s5m8767_para - s5m8767 register parameters
> + * @param vol_addr i2c address of the given buck/ldo register
> + * @param vol_bitpos bit position to be set or clear within register
> + * @param vol_bitmask bit mask value
> + * @param reg_enaddr control register address, which enable the given
> + * given buck/ldo.
> + * @param reg_enbiton value to be written to buck/ldo to make it ON
> + * @param vol Voltage information
> + */
> +struct s5m8767_para {
> + enum s5m8767_regnum regnum;
> + u8 vol_addr;
> + u8 vol_bitpos;
> + u8 vol_bitmask;
> + u8 reg_enaddr;
> + u8 reg_enbiton;
> + const struct sec_voltage_desc *vol;
> +};
> +
> +/* Drivers name */
> +#define S5M8767_LDO_DRIVER "s5m8767_ldo"
> +#define S5M8767_BUCK_DRIVER "s5m8767_buck"
> +
> +int s5m8767_enable_32khz_cp(struct udevice *dev);
> +
> +#endif /* __S5M8767_PMIC_H_ */
>
Acked-by: Przemyslaw Marczak <p.marczak at samsung.com>
Regards
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marczak at samsung.com
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