[U-Boot] [PATCH V2 04/15] imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL
Peng Fan
Peng.Fan at freescale.com
Sat Jul 11 10:07:12 CEST 2015
Since i.MX6UL's cache line size is 64bytes, need to
define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan at freescale.com>
---
Changes v2:
new patch, splitted from patch 03/15.
arch/arm/include/asm/arch-mx6/imx-regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 8f74f19..9f3b3cf 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,11 @@
#define ARCH_MXC
+#ifdef CONFIG_MX6UL
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#else
#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
#define ROMCP_ARB_BASE_ADDR 0x00000000
#define ROMCP_ARB_END_ADDR 0x000FFFFF
--
1.8.4
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