[U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1

[Stephen Warren]

On 07/12/2015 02:10 AM, Alexander Stein wrote:
> On Friday 10 July 2015, 23:17:58 wrote Stephen Warren:
>> On 07/04/2015 03:48 AM, Alexander Stein wrote:
>>> This patchset enables dcache support for Raspberry Pi 1.
>>> First the cache support code was made similar to existing arm1136 code.
>>> The invalidate and flush functions were inprovoed to accept also non-cacheline
>>> aligned addresses. This reduces the cacheline size knowledge from generic
>>> code.
>>
>> As mentioned in some other responses, client code must be aware of the
>> cacheline size, so the cache management code shouldn't try to handle
>> misaligned requests, but should error out.
>>
>> BTW, ALLOC_ALIGN_BUFFER() is probably what you need to fix any
>> misbehaved client code.
> 
> It turns out this is already used everywhere, but the aligned is only 16 instead of 32.

I'm not sure why; is the macro that defines the required alignment
defined incorrectly?

> Is there some neat define for the cache size to be used everywhere without defining it in the board config? This would make no sense as according to ARM1176 TRM the cache size is fixed to 32 bytes.
> So CONFIG_SYS_CACHELINE_SIZE is defined in arch/arm/cpu/arm1176/cpu.c if not defined at board config.

There's ARCH_DMA_MINALIGN, which I'd imagine is equal to the cache line
size in most cases.

> I could use ALLOC_CACHE_ALIGN_BUFFER instead, but this would use an (unnecessary) 64 byte alignment, unless CONFIG_SYS_CACHELINE_SIZE is defined.

Why's that? Is it simply because CONFIG_SYS_CACHELINE_SIZE isn't
defined, so it defaults to 64? If so, I'd suggest simply setting
CONFIG_SYS_CACHELINE_SIZE.